Qualitas Semiconductor
•
HQ:
South Korea
The USB Super-Speed+ PHY IP is a compact and power-efficient interface solution that fully supports the USB 3.2 Gen1 and Gen2 spe…
- Single-Protocol PHY
Compare 1,281 Single-Protocol PHY PIP Cores from 72 vendors
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Qualitas Semiconductor• HQ: South Korea
The 56G/64G PAM4 SERDES hard macro IP delivers a high-performance, low-power solution for high-speed serial interfaces.
- Single-Protocol PHY
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PHY IO for PSRAM memory PHY, 1066Mbps on TSMC 22nm
UniIC• HQ: ChinaThe PHYIOs is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the PSRAM device.
- TSMC
- 22nm
- ULL
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Nuclei System Technology• HQ: China
The USB PHY IP is UTMI interface compatible and a dedicated circuit for full-function USB 2.0 transceivers.
- USB 2.0
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Silicon Library Inc.• HQ: Japan
SLI UHS-II PHY Analog IP consists of a mixed-signal SERDES supporting both Full Duplex and Half Duplex modes.
- PHY
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Obsidian Technology• HQ: USA
USB Full Speed Transceiver
- Single-Protocol PHY
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PCIe 6.0 PHY, SS SF2A x4 1.2V, N/S for Automotive, ASIL B Random, AEC-Q100 Grade 2
Synopsys, Inc.• HQ: USAThe multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency ac…
- Single-Protocol PHY
- Available on request
- Available
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Comcores• HQ: Denmark
Size optimized, Silicon agnostic, Silicon Proven Ethernet PCS IP core for High Speed Ethernet applications The 200G/400G Ethernet…
- Single-Protocol PHY
- Mature
- Available
- IEEE 802.3
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ONFI 5.0 NAND Fash PHY IP Compliant to JEDEC
Arasan Chip Systems Inc.• HQ: USAOpen NAND Flash Interface (ONFI) for NAND Flash Memory chips is an open standard.
- Single-Protocol PHY
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Mixel, Inc.• HQ: USA
The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
- Single-Protocol PHY
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Mixel, Inc.• HQ: USA
The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology.
- Single-Protocol PHY
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Low Latency Ethernet 100G MAC and PHY Intel® FPGA IP Core
Altera• HQ: USAIntel® offers ultimate flexibility, scalability, and configurability with the Low Latency 100G Ethernet Intel® FPGA IP core targe…
- Single-Protocol PHY
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Backplane Ethernet 10GBASE-KR PHY Intel® FPGA IP Core
Altera• HQ: USAThe Backplane Ethernet 10GBASE-KR PHY Intel® FPGA Intellectual Property (IP) core is a transceiver PHY that allows you to instant…
- Single-Protocol PHY
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40G Ethernet MAC and PHY FPGA IP Core
Altera• HQ: USAThe 40G Ethernet MAC and PHY FPGA IP core offers IEEE 802.3ba-2010.
- Single-Protocol PHY
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1G/10Gb Ethernet PHY Intel® FPGA IP
Altera• HQ: USAThe 1G/10G Ethernet PHY Intel® FPGA Intellectual Property (IP) core supports functionality of both the standard physical coding s…
- Single-Protocol PHY
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Multi-Rate Ethernet PHY FPGA IP
Altera• HQ: USAThe Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates without any design regeneration or device re…
- Single-Protocol PHY
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Altera• HQ: USA
The XAUI PHY Intel® FPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection.
- Single-Protocol PHY
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GF12 - 0.8V LVDS Rad-Hard Transceiver in GF 12nm
Certus Semiconductor• HQ: United StatesA radiation-hardened GlobalFoundries 12nm LP/LP+ 0.8V LVDS Transceiver.
- GlobalFoundries
- 12nm
- LP
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Logic Fruit Technologies• HQ: India
The PCIe GEN6 PHY IP achieves data rates up to 64GT/s per lane with PAM4 signaling thereby delivering reliable performance for hi…
- Single-Protocol PHY
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Obsidian Technology• HQ: USA
OT3910bjc is a set of cells designed for implementing the transmitter, receiver and associated bias function for LVDS point to po…
- Single-Protocol PHY