USB 3.1 Type-C PHY IP, Silicon Proven in SMIC 12SF++
A high performance, high-speed SERDES IP known as USB3.1Type-C PHY was created for semiconductors that allow high bandwidth data …
- USB 3.1
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
USB 3.1 Type-C PHY IP, Silicon Proven in SMIC 12SF++
A high performance, high-speed SERDES IP known as USB3.1Type-C PHY was created for semiconductors that allow high bandwidth data …
USB 2.0 PHY IP, Silicon Proven in SMIC 12SF++
A full physical layer (PHY) IP solution designed for outstanding performance and minimal power consumption is the USB2.0 PHY IP.
Silicon Proven 1G Ethernet PHY IP as Whitebox
1G Ethernet PHY IP Core is available for licensing as a Whitebox IP, with unlimited usage and full modification rights granted to…
Silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018 supporting…
The T180BCDLVDSV1 IP is a mini-LVDS TX and RX PHY based on TSMC 180nm BCD process.
The IP is a USB PHY based on TSMC 180nm process.
Silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018 The Ethern…
Silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018 The Ethern…
LVDS Rx IP, Silicon Proven in GF 28LPe
A physical layer IP for LVDS Receiver.
Display Port 1.4 Rx PHY & Controller IP (Silicon Proven in IDM 180nm /150nm)
Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR B…
USB-C 3.1 SS/SSP PHY, Type-C IP (Silicon proven in UMC 55SP/ EF)
A high performance, high-speed SERDES IP called USB3.1Type-C PHY is created for semiconductors that provide high bandwidth data c…
Gigabit Ethernet PHY (Modification Right)
Gigabit Ethernet PHY Modification Right (in production)
ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC)
ONFI PHY block is used to either transmit signal and data to NAND Flash interface or receive the data from NAND Flash by Flash co…
The LVDS transceiver IP is a SERDES pair that clearly interprets 12–bit parallel bus into serial stream.
Special I/O-eMMC/SDIO in TSMC(22nm, 28nm, and 40nm)
SD (Secureity Digital) and eMMC (embedded MultiMedia Card) I/Os are non-volatile memory interface technologiesy with high bandwid…
PCIe 4.0 PHY in TSMC(6nm,7nm, 12nm,16nm)
M31 PCIe 4.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.
ONFI I/O 6.0/5.1/5.0 IP in TSMC(3nm, 5nm, 6nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm)
ONFI I/O is a non-volatile memory interface technology with high bandwidth capabilities, mainly developed for flash storage appli…
The SONY_CAM_IF IP Core provides a simple way to connect the Sony® FCB-EV range of cameras to your FPGA.
Ultra-Low-Latency 10GE PHY+MAC
Having the lowest network latency is critical for Accelerated Finance.
The TRC16024CPA is a four lane Gen 1,2,3,4 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transm…