LVDS Transmitter
The LVDS_TX is CMOS differential line transmitter designed for applications requiring ultra low power dissipation, low noise, and…
Overview
The LVDS_TX is CMOS differential line transmitter designed for applications requiring ultra low power dissipation, low noise, and high data rates. The devices are designed to support data rates in excess of 800 Mbps (400 MHz) utilizing Low Voltage Differential Swing (LVDS) technology
Key features
- Fully integrated, compact design
- +/- 20% Accuracy.
- 3.3V± 10% power supply
- 800Mbps(400Mhz) switching rates
- External termination resistor 100 ohm.
- Area 0.00836 mm2
- CMOS 130nm 1P5M,3.3V IO MOS
- Worst case Power consumption 7.67mA
Benefits
- High switching speed
- Fast time to market
What’s Included?
- GDSII & CDL Netlist
- .lef for PnR
- .libs for Timing
- Datasheet
- Technical Reference Manual, Design Document
Specifications
Identity
Provider
Learn more about Single-Protocol PHY IP core
Casting a wide safety net through post processing Checking
HCLTech and Arm Collaborate on Custom Silicon Chips Optimized for AI Workloads
HCLTech and Arm collaborate on custom silicon chips optimized for AI workloads
UPF Constraint coding for SoC - A Case Study
Low Power Design in SoC Using Arm IP
Frequently asked questions about Single-Protocol PHY IP
What is LVDS Transmitter?
LVDS Transmitter is a Single-Protocol PHY IP core from HCL Technologies listed on Semi IP Hub.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.