Vendor: Soft Mixed Signal Corp. Category: Single-Protocol PHY

Serial ATA (SATA) PHY Transceiver IP

SMS6000 is a fully integrated CMOS transceiver that handles the low level Serial ATA protocol and signaling.

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Overview

SMS6000 is a fully integrated CMOS transceiver that handles the low level Serial ATA protocol and signaling. It contains all necessary Clock synthesis, Clock Recovery, Serializer, Deserializer, Comma detect for 8B/10B encoded data and Frame alignment functionalities. Digital controller interface is realized with a 10-bit parallel operation (Optional 20-bit Interface) that allows use of 150 MHz (300 MHz) reference Clock. The transceiver includes Signal Detect, COMRESET/COMINIT and COMWAKE Out-of-Band capability compliant with Serial ATA Specification requirements in addition to COMSAS Out-of-band Signal detection capability required by the Serial Attached SCSCI (SAS).

SMS6000 complies with the latest version of the SAPIS standard both as a PHY Core IP and for discrete Transceiver implementations.

SMS6000 implements the full requirements of Serial ATA 1.0a specification in terms of Power Management and Loopback functionality. Both Partial and Slumber power management modes are fully supported both in the digital portion and the AFE of the PHY for maximum power efficiency. Also all the Loopback functions such as Near-End Loopback and Far-End-Loopback are supported in addition to proprietary Loopback implementations for functional testing.

SMS6000 does not require any external Loop filter capacitor(s) for clock Synthesis PLL or Clock recovery circuitry making it immune to PCB related noise typically encountered, and provides a completely integrated solution.

Key features

  • Supports 1.5 Gb/s (Gen 1) and 3.0 Gb/s (Gen 2) serial data rate
  • Compatible with Serial ATA II
  • Utilizes 10-bit or 20-bit parallel interface to transmit and receive Serial ATA data
  • Data and clock recovery from serial stream on the SATA bus
  • Optional 8b/10b encode/decode and error indication
  • Near-End and Far-End Loop-back Support
  • Embedded Bit Error Rate Testing Through PBRS generation and detection
  • Supports HOST and DEVICE controller applications
  • OOB Signal Detection for COMWAKE, COMRESET/COMINIT and COMSAS
  • COMMA & Squelch Detect Support
  • Power Management Support for Slumber and Partial PM Modes.
  • Calibrated Internal RX, TX Termination Resistors
  • Support for Serial Attached SCSI SAS Mode
  • Compliant with SATA PHY Interface Specification (SAPIS)
  • Full low cost, low power CMOS Implementation

Block Diagram

SMS6000 block diagram

What’s Included?

  • Bus Functional/Behavioral Model for the PHY.
  • Hard Macro GDS.
  • Netlist for LVS/DRC support.
  • SOC Integration Plan.
  • Test Plan.

Specifications

Identity

Part Number
SMS6000
Vendor
Soft Mixed Signal Corp.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Soft Mixed Signal Corp.

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Frequently asked questions about Single-Protocol PHY IP

What is Serial ATA (SATA) PHY Transceiver IP?

Serial ATA (SATA) PHY Transceiver IP is a Single-Protocol PHY IP core from Soft Mixed Signal Corp. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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