Home Plug Green PHY MAC Layer TX/RX
ntHPGP_MAC IP core implements “Connectionless CSMA-Only Level-0 CCo“ MAC Layer functionality with Passive Coordination, as detail…
- TSMC
- 28nm
- Silicon Proven
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
Home Plug Green PHY MAC Layer TX/RX
ntHPGP_MAC IP core implements “Connectionless CSMA-Only Level-0 CCo“ MAC Layer functionality with Passive Coordination, as detail…
Enables 1.6T and 800G networks
ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+)
ONFI PHY block is used to either transmit signal and data to NAND Flash interface, or receive the data from NAND Flash by Flash c…
LVDS / sub-LVDS / DPHY TX - TSMC 6FFC
The LVDS/Sub-LVDS/DPHY Combo TX converts parallel RGB data and 7/8/10 bits of CMOS parallel data into serial data streams.
LVDS RX & TX IOs in multiple foundry technology
Certus provides full LVDS RX & TX IOs in GlobalFoundries and other foundry technologies.
LVDS 160MHz 8-Lane PHY TX IP on TSMC 16FFC
The CL12491M8TIP160 transmitter converts parallel RGB data and 4bits of HYNC,VSYNC,DE and Control) of CMOS parallel data into ser…
KA13UGUSB20ST001 is USB2.0 physical layer transceiver (PHY) integrated circuits.
USB2.0 PHY(HSIC/Host/Device/OTG/Hub)/ eUSB PHY
USB is the ubiquitous interconnect standard of choice for a wide range of computing and consumer applications.
USB is the ubiquitous interconnect standard of choice for a wide range of computing and consumer applications.
028TSMC_LVDS_01 is a library including: Transmitter LVDS driver (TX_LVDS); Receiver LVDS driver (RX_LVDS); Reduced range link rec…
GbE (10/100 Base-T) PHY IP, Silicon Proven UMC 28HPC
Ethernet PHY is an IEEE 802.3u compliant single-port Ethernet physical layer transceiver, and low power consumption transceiver f…
055TSMC_LVDS_03 is a library including: Transmitter LVDS driver (TX_LVDS); Receiver LVDS driver (RX_LVDS); Reference current/volt…
The KA13ETHB33 is a single-port PHY with an MII (Media Independent Interface).
180TSMC_LVDS_10 is a library including: Transmitter LVDS driver (TX_LVDS); Receiver LVDS driver (RX_LVDS); Transceiver LVDS drive…
Display Port 1.2 Tx PHY & Controller IP (Silicon Proven in STMicro 28FDSOI)
Our Display Port is VESA DP1.1a, DP1.2 and eDP compliant with four main lanes and an auxiliary channel The DP transmitter accepts…
2 Gbps Rail to Rail LVDS receiver
065TSMC_LVDS_10 is LVDS receiver with rail to rail input range.
10/25/40/100Gbit/s Ethernet PCS/PMA
Smooth integration of TCP/IP and UDP/IP protocols in your FPGA PGA Synthesisable 10/25/40/100 Gbit/s Ethernet PCS code for ultra-…
1.2 Gbps LVDS transmitter/receiver
The interface to the core logic in receiver mode includes the signal pins (out_p and out_n) to receive data and the control pins …
1 Gbps Rail to Rail LVDS receiver
065TSMC_LVDS_08 is LVDS receiver with rail to rail input range.
065TSMC_LVDS_07 is LVDS transmitter.