Vendor: Cadence Design Systems, Inc. Category: Single-Protocol PHY

Low-Speed Ethernet PCS

Integrates MAC IP to a broad range of PHY and SerDes IP

Overview

Cadence Ethernet PCS and connectivity IP provide you with a wide range of connectivity IP that can be used to interface Cadence and third-party MAC IP to standard interfaces. Our Ethernet PCS solutions ease integration of MAC IP with a broad range of PHY and SerDes IP. Our connectivity IP solutions include XGMII to GMII converters and Backplane Ethernet Auto-Negotiation (BEAN).

Key features

USXGMII PCS 

  • Multi-speed with Clause 37-type auto-negotiation
  • Configurable as 5GBASE-R or 10GBASE-R compliant with IEEE 802.3 Clauses 49 and 129

XAUI PCS

  • Available in 10-bit and 20-bit datapath versions
  • Optional 1Gb/s mode with 4x GMII channels

Block Diagram

Ethernet PCS IP block diagram

Benefits

  • Mature: Silicon-proven design in volume production at multiple customers
  • Ease-of-use: Customizable with easy integration
  • Designed by an Industry Leader: Cadence is an active contributor to the IEEE 802.3 standards working groups

Specifications

Identity

Part Number
Low-Speed Ethernet PCS
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP

Files

Product Sheet Download

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Provider

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Frequently asked questions about Single-Protocol PHY IP

What is Low-Speed Ethernet PCS?

Low-Speed Ethernet PCS is a Single-Protocol PHY IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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