IP
- SMIC
- 40nm
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
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USB 3.1 is the most recent version of the USB (Universal Serial Bus) standard for connecting electronic devices in host and devic…
OT3910bj is a set of cells designed for implementing the transmitter, receiver and associated bias function for LVDS point to poi…
The TRC5024CPA is a four lane Gen 1 and 2 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transmi…
USB 1.1 PHY in TSMC(40nm, 55nm, 90nm ULP process )
M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.
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USB2.0 PHY - SMIC 110nm generic
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USB 2.0 PHY - SMIC 55nm Eflash
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USB 2.0 PHY - SMIC 55nm Eflash
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USB 1.1/2.0 full speed USB PHY
T25201 is a and high integrated USB 2.0 low speed and full speed transceiver implementing the physical layer of a USB compliant d…
Aurora-like 64b/66b @14Gbps for ALTERA Devices
REFLEX CES introduces a release at 14Gbps of its Aurora-like IP Core based on ALTERA FPGA enabling interoperability between XILIN…
LVDS transmitter - TowerJazz 0.13um
LVDS transmitter