LVDS Receiver
The LVDS_RX is CMOS differential line receivers designed for applications requiring ultra low power dissipation, low noise, and h…
Overview
The LVDS_RX is CMOS differential line receivers designed for applications requiring ultra low power dissipation, low noise, and high data rates. The devices are designed to support data rates in excess of 800 Mbps (400 MHz) utilizing Low Voltage Differential Swing (LVDS) technology
The LVDS_RX accept low voltage (±50 mV typical) differential input signals and translates them to 3.3V CMOS output levels. The receivers also support open, shorted, and terminated (100Ω) input fail-safe. The receiver output will be HIGH for all fail-safe conditions
Key features
- Fully integrated, compact design
- 800Mbps(400Mhz) switching rates
- 60ps differential skew
- 1.15ns Maximum propagation delay
- Single 3.3V power supply (3.0V to 36V range)
- Accepts small swing (±50mv typical) differential signal
- Support open, short and terminated input fail-safe
- Low Power Dissipation (5.01mA @ 3.6V static)
Benefits
- High switching speed
- Low differential skew
- Less propagation delay
- Accept small swing in differential signal
- Fast time to market
What’s Included?
- GDSII & CDL Netlist
- .lef for PnR
- Datasheet
- Technical Reference Manual, Design Document
Specifications
Identity
Provider
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Frequently asked questions about Single-Protocol PHY IP
What is LVDS Receiver?
LVDS Receiver is a Single-Protocol PHY IP core from HCL Technologies listed on Semi IP Hub.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.