Vendor: HCL Technologies Category: Single-Protocol PHY

LVDS Receiver

The LVDS_RX is CMOS differential line receivers designed for applications requiring ultra low power dissipation, low noise, and h…

Contact Provider Request Datasheet

Overview

The LVDS_RX is CMOS differential line receivers designed for applications requiring ultra low power dissipation, low noise, and high data rates. The devices are designed to support data rates in excess of 800 Mbps (400 MHz) utilizing Low Voltage Differential Swing (LVDS) technology
The LVDS_RX accept low voltage (±50 mV typical) differential input signals and translates them to 3.3V CMOS output levels. The receivers also support open, shorted, and terminated (100Ω) input fail-safe. The receiver output will be HIGH for all fail-safe conditions

Key features

  • Fully integrated, compact design
  • 800Mbps(400Mhz) switching rates
  • 60ps differential skew
  • 1.15ns Maximum propagation delay
  • Single 3.3V power supply (3.0V to 36V range)
  • Accepts small swing (±50mv typical) differential signal
  • Support open, short and terminated input fail-safe
  • Low Power Dissipation (5.01mA @ 3.6V static)

Benefits

  • High switching speed
  • Low differential skew
  • Less propagation delay
  • Accept small swing in differential signal
  • Fast time to market

What’s Included?

  • GDSII & CDL Netlist
  • .lef for PnR
  • Datasheet
  • Technical Reference Manual, Design Document

Specifications

Identity

Part Number
HCLLVDSRCV170310
Vendor
HCL Technologies
Type
Silicon IP

Provider

HCL Technologies
HQ: India
Contact HCL Technologies

Learn more about Single-Protocol PHY IP core

UFS Goes Mainstream

UniversalFlash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniPro as well as eMMC form factors to simplify adoption and development.

Design IP Faster: Introducing the C~ High-Level Language

In this paper, we introduce a new high-level, dataflow programming language called C~ (“C flow”) that further increases productivity by raising the level of abstraction from behavioral descriptions, while overcoming the limitations of C for hardware design. We present the syntax and semantics of this language, and the framework that provides hardware and software code generation. This paper illustrates the benefits of using C~ for hardware design of a IEEE 802.3 MAC, synthesized for FPGA and for 90nm CMOS technology.

Universal Flash Storage: Mobilize Your Data

Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

Can MIPI and MDDI Co-Exist?

Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

Frequently asked questions about Single-Protocol PHY IP

What is LVDS Receiver?

LVDS Receiver is a Single-Protocol PHY IP core from HCL Technologies listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP