Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core
By Benjamin Hubinet 1,2, Pierre-Alain Moëllic 1,2, Olivier Savry 2, Olivier Potin 3, Jean-Baptiste Rigaud 3
1 CEA-Leti, Mines Saint-Etienne, Equipe Commune SAS, F-13541 Gardanne, France
2 Univ. Grenoble Alpes, CEA-Leti, F-38000 Grenoble, France
3 Mines Saint-Etienne, CEA-Leti, Centre CMP, Equipe commune SAS, F-13541 Gardanne, France
Abstract
By leveraging standard RISC-V extensions, namely Zfh (scalar float16) and Zvfh (vector float16), this work proposes an open-source framework to enable complete on-device training on resource-constrained RISC-V single-core. Our approach allows memory footprint reduction by about 50% as compared to using float32 and with minimal model performance degradation. We also facilitate transfer learning and fine-tuning scenarios by incorporating layer-freezing capabilities. Our work builds onto AIfES, an open-source, modular and generic DNN training and inference framework for embedded systems that can be extended with custom hardware-specific functions. The benefits of float16 is further emphasized by outlining the low area overhead of Zfh on a RV64GC super-scalar out-of-order FPGA softcore (+1.15% LUT6 and +0.05% FF at 175MHz). Finally, we discuss the architecture of a Zvfh implementation within the same RISC-V core.
Keywords: On-Device Training, Half-Precision Floating-Point, RISC-V, Deep Neural Networks, Resource-Constrained Devices, FPGA.
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