A Heterogeneous Neural Network Accelerator for End-to-End Multitask RF Signal Recognition
By Zhifan Song, Haralampos-G. Stratigopoulos, and Hassan Aboushady
Sorbonne University, CNRS, LIP6, Paris, France

Abstract
This paper presents a heterogeneous neural network accelerator for multi-task RF signal recognition, supporting automatic modulation recognition (AMR), hardware-Trojan covert channel (HT-CC) detection, and GNSS jamming classification. We introduce a compact attention-enhanced convolutional neural network (CNN) combined with LSDec, a learnable streaming decimator that enables adaptive temporal downsampling and flexible input lengths. The hardware architecture integrates a novel dual-pipeline, fused convolution-pooling engine with DMA-based streaming to minimize memory traffic and latency. Co-execution scheduling on the accelerator and SIMD-optimized CPU kernels reduces hardware resource usage while preserving high performance and task-level flexibility. Across three datasets, the proposed system achieves ≥ 99% average accuracy above 4 dB Signal-to-Noise Ratios (SNRs) on the RadioML2018 dataset for AMR, 90% on the HT-CC dataset, and 99.5% on the GNSS-Jamming dataset. The accelerator sustains an end-to-end inference latency of 98 μs per frame, demonstrating its effectiveness for low-power, latency-critical multi-task spectrum-intelligence applications on embedded and edge devices.
To read the full article, click here
Related Semiconductor IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
- UCIe 2.x Controller IP
- SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
- OpenTitan-based RISC-V Secure Element
Related Articles
- MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks
- AceleradorSNN: A Neuromorphic Cognitive System Integrating Spiking Neural Networks and Dynamic Image Signal Processing on FPGA
Latest Articles
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM
- MEGATRON: a 28nm Analog PCM CiM/Digital System-on-Chip for Edge GenAI at 57.5 TOPS/W and 1.52 Mparam/mm²
- Peregrino: A Full-Hardware Accelerator for the Complete Falcon Post-Quantum Digital Signature Scheme on Resource-Constrained Edge Devices