A Heterogeneous Neural Network Accelerator for End-to-End Multitask RF Signal Recognition
By Zhifan Song, Haralampos-G. Stratigopoulos, and Hassan Aboushady
Sorbonne University, CNRS, LIP6, Paris, France

Abstract
This paper presents a heterogeneous neural network accelerator for multi-task RF signal recognition, supporting automatic modulation recognition (AMR), hardware-Trojan covert channel (HT-CC) detection, and GNSS jamming classification. We introduce a compact attention-enhanced convolutional neural network (CNN) combined with LSDec, a learnable streaming decimator that enables adaptive temporal downsampling and flexible input lengths. The hardware architecture integrates a novel dual-pipeline, fused convolution-pooling engine with DMA-based streaming to minimize memory traffic and latency. Co-execution scheduling on the accelerator and SIMD-optimized CPU kernels reduces hardware resource usage while preserving high performance and task-level flexibility. Across three datasets, the proposed system achieves ≥ 99% average accuracy above 4 dB Signal-to-Noise Ratios (SNRs) on the RadioML2018 dataset for AMR, 90% on the HT-CC dataset, and 99.5% on the GNSS-Jamming dataset. The accelerator sustains an end-to-end inference latency of 98 μs per frame, demonstrating its effectiveness for low-power, latency-critical multi-task spectrum-intelligence applications on embedded and edge devices.
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