Hybrid ASIC-FPAA Fabric for Performance Security Trade-off

By Ziyi Chen, Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis
Drexel University, Philadelphia

Abstract

In this paper, a hybrid architecture that combines an application specific integrated circuit (ASIC) and a field-programmable analog array (ASIC-FPAA) is proposed to address the performance-security trade-off in analog circuits. A programmable transistor pair (TP) is developed that obfuscates the topology of an analog circuit within an array of transistor pairs while minimizing the degradation in circuit performance due to the implemented security features. In addition, a technique that utilizes dummy transistor pairs is proposed that further masks the topology of a circuit by obfuscating the number of active transistors that comprise the target analog circuit. A method to obfuscate the entire topology of an analog circuit is also developed. The FPAA provides the highest-level of security robustness as the entire circuit topology is programmed onto the transistor pair array, while trading-off performance. For large analog circuits requiring multiple configurable analog blocks (CABs), an algorithm is developed that identifies and maps the sub-blocks of the circuit best suited for obfuscation on the FPAA fabric, while accounting for the trade-off between performance and security. For the delta-sigma modulator, the comparator module is selected for implementation on the FPAA fabric, which results in a reduction of less than 0.25% in the effective number of bits (ENOB) and an increase of 28.1% in the power consumption as compared to an unobfuscated delta-sigma modulator. The security robustness of the proposed techniques are evaluated against the latest attack methodologies. Results indicate that the proposed techniques provide a 5x improvement in security as measured by a developed metric without compromising performance.

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