Reducing Instruction-Fetch Energy in RISC-V for Embedded AI Processing via Dynamic and Static Loop Caching
By Wiebren Wijnstra, Sameed Sohail, Berend-Jan van der Zwaag, Sabih Gerez, Amirreza Yousefzadeh
University of Twente, Enschede, The Netherlands
Abstract
Embedded RISC-V processors are increasingly deployed for on-device AI inference at the edge, where energy efficiency is a primary design constraint. Instruction fetching from SRAM-based memory is a dominant source of energy consumption in these cores, accounting for over 40% of total energy in our baseline measurements. This paper presents two loop cache architectures integrated into the datapath of a RISC-V processor: a dynamic loop cache that automatically detects and caches short backward-branch loops at runtime, and a static loop cache that functions as a software-managed hot-code instruction buffer, allowing preloading of arbitrary instruction blocks during the boot sequence. Both designs are implemented in the open-source NEORV32 RISC-V processor and evaluated on a LeNet-5 convolutional neural network inference workload, synthesized on GlobalFoundries 22nm FDX+ technology at 0.5V and 250MHz. The dynamic cache reduces instruction fetches by 48.3% and total energy by 21.5%, while the static cache achieves an 83.3% fetch reduction and 35.5% total energy savings. The area overhead of both designs remains below 0.2% of the full SoC area. The complete implementation is open source: https://github.com/wwiebren/NEORV32_loopcache_for_SparkRV.
Index Terms — RISC-V, loop cache, energy efficiency, instruction fetch, embedded AI processor, low-power edge inference
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