Lattice Semiconductor Corp. IP Cores

Video edge detection is the process of calculating gradients (rates of change) in pixel values in an incoming frame.

• Video Processing

Direct Memory Access (DMA) is a technique for transferring blocks of data between system memory and peripherals without a process…

• DMA

Gamma correction is a type of pre-distortion correction made to images or video frames to offset the non-linear behavior of displ…

• Image Conversion

Serial Digital Interface (SDI) is the most popular raw video connectivity standard used in television broadcast studios and video…

• Video Transport

The SPI4 Intellectual Property (IP) core enables user instantiation of OIF-compliant System Packet Interface Level 4 Phase 2 Revi…

• Ethernet

Numerically Controlled Oscillators (NCO), also called Direct Digital Synthesizers (DDS), offer several advantages over other type…

• Oscillator

The function of this core is to correlate an incoming data stream to a stored binary pattern called a code sequence or coefficien…

• Filters Transforms

CORDIC (COordinate Rotation DIgital Computer) is a simple and efficient algorithm to calculate hyperbolic and trigonometric funct…

• Arithmetic Units

Cascaded Integrator-Comb (CIC) filters, also known as Hogenauer filters, are used to achieve arbitrary and large sample rate chan…

• Filters Transforms

As the proliferation of HDTV, IPTV and VoD streaming continues, together with the increased functionality and decreasing costs of…

• Video Transport

JEDEC Standard No.

• JESD204

PCI Express is a high performance, fully scalable, well defined standard for a wide variety of computing and communications platf…

• PCI Express

Digital Video Broadcasting (DVB) is a suite of open standards for digital television.

• Video Transport

The SFI-5 Intellectual Property (IP) core enables user instantiation of an OIF-compliant SERDES Framer Interface Level 5 (SFI-5) …

• Ethernet

This document provides technical information about the Lattice Common Public Radio Interface (CPRI) IP core.

• CPRI

10Gb Ethernet Attachment Unit Interface or XAUI is a high-speed interconnect that offers reduced pin count and has the ability to…

• Single-Protocol PHY

The 2.5Gb MAC core can support data rates of 1Gbps or 2.5Gbps in LatticeSC/M™ devices.

• Ethernet

The LatticeMico32™ is a 32-bit Harvard, RISC architecture "soft" microprocessor, available for free with an open IP core licensin…

• CPU

Soft errors occur when high-energy charged particles alter the stored charge in a memory cell in an electronic circuit.

• Channel Coding

The HiGig™ MAC transmits and receives data between a host processor and a HiGig™ / Ethernet network that enables networking custo…

• Ethernet