Overview
Gamma correction is a type of pre-distortion correction made to images or video frames to offset the non-linear behavior of display systems, such as cathode ray tube (CRT) displays. A characteristic of CRT displays is that the intensity they generate is not a linear function of the input voltage. Instead, the intensity is proportional to a power of the signal amplitude, also referred to as gamma. Gamma is usually greater than 1 and therefore the displays have a lower gain at low intensities and progressively larger gain at higher intensities. The Gamma Corrector IP core multiplies the input signal with the inverse of the display transfer function which results in a linear intensity response with respect to the original input signal.
Several gamma correction methods and values are used in television and display systems. Plasma, LCOS (Liquid Crystal on Silicon) and DLP (Digital Light Processing) displays have transfer characteristics that are different from that of CRT displays. Sometimes the display itself can have linear characteristics, but a gamma transformation (usually called degamma) may be required because of an earlier gamma correction made to the incoming signal.
The Gamma Corrector IP core is a widely parameterizable, multi-color plane gamma correction system. It can support almost any custom gamma correction requirement.
Learn more about Image Conversion IP core
Computer vision has made tremendous advances in the last several years due to the proliferation of AI technology. The intersection of big data and massive parallel computing changed the way in which machines are programmed to understand unstructured 2D and 3D data, such as video feeds from cameras.
Traditional IC design options that embedded system designers have had to choose from include fixed hardware devices such as standalone microprocessors, microcontrollers and ASSPs or configurable hardware devices such as FPGAs and cell-based ASICs. In this paper we present a new design option called Nextreme Structured ASICs which provide embedded system designers with a compelling alternative to custom embedded system design.
By Hantro
Configurable Processors for Video Processing SOCs
In this article, we show how fast video streams conforming to MIPI CSI2 rev2.0 over MIPI DPHY rev1.2 can be generated, using VLSI Plus’ SVTPlus-CSI2-F IP core, with simple off-FPGA analog front-end. The high bit rates can be achieved with a relatively slow FPGA clock frequency, trading off FPGA resources for simple timing closure.
Beyond pure process scaling which is necessary to meet today's price, power, and performance goals, chip designers have to grapple with tighter integration and product performance specialities in areas such as integrated power management, image sensing, application-specific data conversion, and enhanced display drivers.
