FPGA-based Ethernet switches for real-time applications
Lattice Semiconductor and Flexibilis have released a Gigabit Ethernet Switch IP core that is scalable, non-blocking, and extensible
Vendor:
Lattice Semiconductor Corp.
Category:
Ethernet
SFI-5
The SFI-5 Intellectual Property (IP) core enables user instantiation of an OIF-compliant SERDES Framer Interface Level 5 (SFI-5) …
Overview
The SFI-5 Intellectual Property (IP) core enables user instantiation of an OIF-compliant SERDES Framer Interface Level 5 (SFI-5) core in LatticeSC/M Field Programmable Gate Arrays (FPGAs). The SFI-5 System Reference Model is shown in the figure below. The SFI-5 defines a communications interface for a 40 Gbps optical link which typically consists of a Framer, FEC (Forward Error Correction) Processor, and SERDES. The purpose of the SFI-5 interface is to transmit data across multiple channels in parallel, where channels may incur different skews between the transmitter and receivers. The SFI-5 receiver delays the data received on all of the channels to match that channel which incurred the longest delay. This removes any skew variation between the channels.
The SFI-5 interface uses 16 bi-directional SERDES links to transmit and receive data. Another SERDES link (the 17th channel) is used as the Deskew channel.
The SFI-5 is a user-configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that bitstream generation may be prevented or the bitstream may have time logic present unless a license for the IP is procured.
SFI-5 IP User's Guide The LatticeSC SFI-5 IP Core User's Guide is now available.
SFI-5 Evaluation Board The LatticeSC SFI-5 Evaluation Board is a functional platform for development and rapid prototyping of applications that incorporate high-performance SFI-5 interfaces available for SFI-5 evaluation.
SFI-5 Reference Design The reference design included with the SFI-5 IP package (sfi5_eval directory) is designed for use on the LatticeSC SFI-5 Evaluation Board.
The SFI-5 interface uses 16 bi-directional SERDES links to transmit and receive data. Another SERDES link (the 17th channel) is used as the Deskew channel.
The SFI-5 is a user-configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that bitstream generation may be prevented or the bitstream may have time logic present unless a license for the IP is procured.
SFI-5 IP User's Guide The LatticeSC SFI-5 IP Core User's Guide is now available.
SFI-5 Evaluation Board The LatticeSC SFI-5 Evaluation Board is a functional platform for development and rapid prototyping of applications that incorporate high-performance SFI-5 interfaces available for SFI-5 evaluation.
SFI-5 Reference Design The reference design included with the SFI-5 IP package (sfi5_eval directory) is designed for use on the LatticeSC SFI-5 Evaluation Board.
Key features
- The SFI-5 core is fully compliant with the Optical Internetworking Forum (OIF) Implementation Agreement OIF-SFI5-01.02
- Data path uses 17 SERDES transceivers operating in 8-bit only mode
- Sixteen 16-bit wide internal receive and transmit data paths
- Supported through ispLEVER IPexpress for easy user configuration and parameterization
- Included reference design suitable for use on the LatticeSC SFI-5 Evaluation Board with SERDES channels running at 2.5 Gbps
- Reference design uses the Reveal™ Logic Analyzer to observe circuit operation
- User-settable parameters to select the allowed number of framing errors for the deskew channel framer to go into or out of locked state
Block Diagram
SFI-5 block diagram
Specifications
Identity
Part Number
SFI-5
Vendor
Lattice Semiconductor Corp.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about Ethernet IP cores
What is SFI-5?
SFI-5 is a Ethernet IP core from Lattice Semiconductor Corp. listed on Semi IP Hub.
How should engineers evaluate this Ethernet?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.