What is JESD204A IP Core?
JESD204A IP Core is a JESD204 IP core from Lattice Semiconductor Corp. listed on Semi IP Hub.
Vendor:
Lattice Semiconductor Corp.
Category:
JESD204
JESD204A IP Core
JEDEC Standard No.
Overview
JEDEC Standard No. 204A (JESD204A) describes a serialized interface between data converters and logic devices. It contains the information necessary to allow designers to implement devices which can communicate with other devices that are compliant with the standard. Lattice’s JESD204A IP Core offerings support both an Rx core (ADC to FPGA direction) and/or a Tx core (FPGA to DAC direction). The Rx and Tx cores can each be generated separately and with different parameters.
Key features
- Compliant with JEDEC Standard No. 204A (JESD204A) April 2008
- Rx core performs lane alignment buffering / detection / monitoring and correction
- Rx core performs frame alignment detection / monitoring and octet reconstruction
- Rx core performs user-enabled descrambling
- Rx core recovers link configuration parameters during initial lane synchronization and compares them to userselected parameters to generate a configuration mismatch error
- Tx core performs user-enabled scrambling
- Tx core generates initial lane alignment sequence
- Tx core performs alignment character generation
- Tx core sources link configuration data with user selected parameter values during initial lane synchronization sequence
Block Diagram
JESD-204A block diagram
Specifications
Identity
Part Number
JESD-204A
Vendor
Lattice Semiconductor Corp.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Frequently asked questions about JESD204 IP cores
How should engineers evaluate this JESD204?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this JESD204 IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.