Lattice Semiconductor Corp. IP Cores

The latest trend in portable computer power management is Switchable Graphics.

• MIPI

Lattice DFE (Digital Front End) demo provides a digital solution consisting of CPRI (Common Public Radio Interface), DUC (Digital…

• Filters Transforms

The Deinterlacer IP core converts input video stream from interlaced format into progressive format and uses bob, intra and inter…

• Video Processing

The Lattice Double Data Rate (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory contr…

• Controller
• DDR3

The Lattice Double Data Rate (DDR3) Physical Interface (PHY) IP is a general-purpose IP that provides connectivity between a DDR3…

• Controller + PHY + 1
• DDR3

The DDR/DDR2 Synchronous Dynamic Random Access Memory (SDRAM) Controller MACO Core is a general-purpose memory controller that in…

• Controller
• DDR2

DDR (Double Data Rate) SDRAM was introduced as a replacement for SDRAM memory running at bus speeds over 75MHz.

• Controller

This version of the Lattice DDR SDRAM Controller does not have pipelining, and is significantly smaller than the pipelined versio…

• Controller

As stated by the CSIX Forum, the CSIX standard defines the physical and message layers of the interconnect between traffic manage…

• Protocol Bridge

As stated by the CSIX Forum, the CSIX standard defines the physical and message layers of the interconnect between traffic manage…

• Protocol Bridge

Convolutional encoding is a process of adding redundancy to a signal stream.

• Channel Coding

Color Space Converters (CSC) are used in video and image display systems including televisions, computer monitors, color printers…

• Image Conversion

Many traditional image sensors have a CMOS interface.

• MIPI

The 2D Scaler IP core converts input video frames of one size to output video frames of a different size.

• Video Processing

The Lattice 2.5 Gbps Ethernet PCS IP core implements the state machine functions for the physical coding sublayer (PCS) described…

• Single-Protocol PHY

The 2.5GMAC IP core supports the ability to transmit and receive data between a host processor and an Ethernet network.

• Ethernet

The GbE PCS Intellectual Property (IP) Core targets the programmable array section of the ORCA ORT42G5 FPSC and provides the PCS …

• Single-Protocol PHY

The 10 Gigabit Ethernet Extended Sublayer (XGXS) Intellectual Property (IP) Core enables the creation of system solutions for 10 …

• Single-Protocol PHY

The 10 Gigabit Ethernet (10 GbE) Physical Coding Sublayer (PCS) solution from Lattice Semiconductor enables creation of system so…

• Single-Protocol PHY

The 2D FIR Filter IP core performs real-time 2D convolution of windowed portions of incoming video frames with coefficient matric…

• Filters Transforms