Vendor: Lattice Semiconductor Corp. Category: Single-Protocol PHY

10Gb Ethernet PCS

The 10 Gigabit Ethernet (10 GbE) Physical Coding Sublayer (PCS) solution from Lattice Semiconductor enables creation of system so…

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Overview

The 10 Gigabit Ethernet (10 GbE) Physical Coding Sublayer (PCS) solution from Lattice Semiconductor enables creation of system solutions for applications using 10 Gigabit Ethernet as defined by IEEE 802.3ae. This IP solution includes soft IP that is targeted to the programmable array section of the ORCA® ORLI10G FPSC. The ORLI10G contains a 10 Gbits/s Transmit and Receive Line Interface, and when combined with this PCS core, enables flexible10GbE LAN/WAN application solutions.

The 10 GbE PCS IP solution includes a 10GbE scrambler/descrambler, 10 GbE Media Independent Interface (XGMII) and 64b/66b encoder/decoder functions. These functions are implemented in software to provide flexibility while the specifications for these interface functions are being finalized. This IP interfaces with the high-speed line interface block embedded in the ORLI10G which implements an OIF standard (OIF 99.102.5) 10Gb 16-bit Interface (XSBI).

The PCS IP is provided in ORCA bitstream format to allow direct downloading and turnkey functionality. Simulation models, test benches and documentation are also provided to support customers in integrating the functions for 10 GbE LAN/WAN applications.

Key features

  • Complete 10Gb Ethernet Physical Coding Sublayer (PCS) Solution Based on the ORCA 10 Gbits/s Line Interface (ORLI10G) FPSC, Enabling Flexible10GbE LAN/WAN Application Solutions.
  • IP Targeted to the ORLI10G Programmable Array Section Implements Functionality Conforming to IEEE Standard 802.3ae, Including:
    • 10 GbE Media Independent Interface (XGMII) for Interfacing with 10Gb Ethernet MACs.
    • Elastic Store Buffers for Clock Domain Transfer to/from the XGMII Interface.
    • X58 + X39 + 1 Polynomial 10GbE Scrambler/ Descrambler Blocks.
    • Receive Direction 64b-to-66b Gearbox, 66-bit Word Aligner and 64b/66b Decoder.
    • Transmit Direction 64b/66b Encoder and 66b-to-64b Gearbox.
    • Interface with the High-speed Line Interface Block Embedded in the ORLI10G which Implements an OIF Standard (OIF 99.102.5) 10Gb 16-bit Interface (XSBI).
  • ORCA Bitstream Format Allows Direct Downloading and Turnkey Functionality.
  • ModelSim Simulation Models and Test Benches Available for Free Evaluation.

Block Diagram

10GBE-PCS block diagram

Specifications

Identity

Part Number
10GBE-PCS
Vendor
Lattice Semiconductor Corp.
Type
Silicon IP

Files

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Provider

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Frequently asked questions about Single-Protocol PHY IP

What is 10Gb Ethernet PCS?

10Gb Ethernet PCS is a Single-Protocol PHY IP core from Lattice Semiconductor Corp. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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