Vendor: Lattice Semiconductor Corp. Category: Single-Protocol PHY

XAUI 10Gb Ethernet Attachment Unit Interface

10Gb Ethernet Attachment Unit Interface or XAUI is a high-speed interconnect that offers reduced pin count and has the ability to…

Overview

10Gb Ethernet Attachment Unit Interface or XAUI is a high-speed interconnect that offers reduced pin count and has the ability to drive up to 20 inches of PCB trace on standard FR-4 material. Each XAUI interface comprises four self-timed 8b10b encoded serial lanes each operating at 3.125 Gbps and thus is capable of transferring data at an aggregate rate of 10 Gbps.

XAUI IP Core provides a solution for bridging between XAUI and 10 Gigabit Media Independent Interface (XGMII) devices. This IP core implements 10Gb Ethernet Extended Sublayer (XGXS) capabilities in soft logic that together with PCS and SERDES functions implemented in the FGPA provides a complete XAUI-to-XGMII solution.

Key features

  • XAUI compliant functionality supported by embedded SERDES PCS functionality implemented in the LatticeECP2M and LatticeECP3, including four channels of 3.125 Gbps serializer/deserializer with 8b10b encoding/decoding.
  • Complete 10Gb Ethernet Extended Sublayer (XGXS) solution based on LatticeECP2M and LatticeECP3 FPGA.
  • Soft IP targeted to the FPGA implements XGXS functionality conforming to IEEE 802.3ae-2002, including:
    • 10 GbE Media Independent Interface (XGMII).
    • Optional Slip buffers for clock domain transfer to/from the XGMII interface.
    • Complete translation between XGMII and XAUI PCS layers, including 8b10b encoding and decoding of Idle, Start, Terminate, Error and Sequence code groups and sequences, and randomized Idle generation in the XAUI transmit direction.
    • XAUI compliant lane-by-lane synchronization.
    • Lane deskew functionality.
    • Interface with the high-speed SERDES block embedded in the LatticeECP2M and LatticeECP3 that implements a standard XAUI.
    • Optional standard compliant MDIO/MDC interface.
  • Aldec and ModelSim simulation models and test benches provided for free evaluation.

Block Diagram

XAUI block diagram

Specifications

Identity

Part Number
XAUI
Vendor
Lattice Semiconductor Corp.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Single-Protocol PHY IP core

Using FPGAs to build a compact, low cost, and low power Ethernet-to-Network Processor bridge

As carriers and cable providers begin rolling out triple-play and VoD services to their customers, OEMs are increasing their development efforts to roll out IP- (Internet Protocol) based systems, including PONs, CMTS, IP DSLAMs and other access and last-mile equipment. The common underlying physical layer for this is the ubiquitous Ethernet technology, now coupled with sophisticated QoS (Quality of Service) overlays.

Frequently asked questions about Single-Protocol PHY IP

What is XAUI 10Gb Ethernet Attachment Unit Interface?

XAUI 10Gb Ethernet Attachment Unit Interface is a Single-Protocol PHY IP core from Lattice Semiconductor Corp. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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