Lattice Semiconductor Corporation provides the industry’s broadest range of Programmable Logic Devices ( PLD), including Field Programmable Gate Arrays ( FPGA), Complex Programmable Logic Devices ( CPLD), Mixed-Signal Power Management and Clock Generation Devices, and industry-leading SERDES products.
LatticeMico32 Open, Free 32-Bit Soft Processor
The LatticeMico32™ is a 32-bit Harvard, RISC architecture "soft" microprocessor, available for free with an open IP core licensin…
Soft errors occur when high-energy charged particles alter the stored charge in a memory cell in an electronic circuit.
The HiGig™ MAC transmits and receives data between a host processor and a HiGig™ / Ethernet network that enables networking custo…
Tri-Speed Ethernet MAC Core IP
The Tri-Speed Ethernet Media Access Controller (TSMAC) IP core can be configured to operate in either the Gigabit mode (1000Mbits…
DDR2 SDRAM Controller - Pipelined
The Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller tha…
DDR SDRAM Controller - Pipelined
The Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller tha…
Interleaving is a technique commonly used in communication systems to overcome correlated channel noise such as burst error or fa…
The Lattice SGMII and Gb Ethernet PCS IP core implements the PCS functions of both the Cisco SGMII and the IEEE 802.3z (1000BaseX…
Peripheral Component Interconnect (PCI) is a widely accepted bus standard that is used in many applications including telecommuni…
Dynamic Block Reed-Solomon Encoder
Reed-Solomon codes are used to perform Forward Error Correction (FEC).
Dynamic Block Reed-Solomon Decoder
Reed-Solomon codes are used to perform Forward Error Correction (FEC).
Convolutional encoding is a process of adding redundancy to a signal stream to provide error correction capability.
Turbo coding is an error correction technique widely used in the communications industry.
Turbo coding is an error correction technique widely used in the communications industry.
Distributed Arithmetic FIR (DA-FIR) Filter Generator
The Lattice Distributed Arithmetic Finite Impulse Response (DA-FIR) Filter Generator IP implements a configurable, multi-channel …
Viterbi decoding is an efficient algorithm for decoding convolutionally encoded sequences corrupted by channel noise back to the …
Lattice's FFT Compiler offers forward and inverse Fast Fourier Transforms for point sizes from 64 to 16384.
Peripheral Component Interconnect (PCI) is a widely accepted bus standard that is used in many applications including telecommuni…
The 10Gb+ Ethernet Media Access Controller (MAC) transmits and receives data between a host processor and an Ethernet network.
Peripheral Component Interconnect (PCI) is a widely accepted bus standard that is used in many applications including telecommuni…