Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
USB 2.0 femtoPHY in UMC (28nm, 22nm)
The Synopsys IP USB 2.0 femtoPHY provides designers with a physical (PHY) layer IP solution for low-power mobile and consumer app…
HDMI - Display Port Combo PHY IP, Silicon Proven in TSMC 28HPC+
The DisPlay Port/HDMI/DVI Receiver is a high performance combo PHY with Display Port Receiver and HDMI Receiver.
Display Port 1.2 Tx PHY & Controller IP (Silicon Proven in STMicro 28FDSOI)
Our Display Port is VESA DP1.1a, DP1.2 and eDP compliant with four main lanes and an auxiliary channel The DP transmitter accepts…
2 Gbps Rail to Rail LVDS receiver
065TSMC_LVDS_10 is LVDS receiver with rail to rail input range.
USB 2.0 femtoPHY in SMIC (40nm, 28nm)
The Synopsys IP USB 2.0 femtoPHY provides designers with a physical (PHY) layer IP solution for low-power mobile and consumer app…
10/25/40/100Gbit/s Ethernet PCS/PMA
Smooth integration of TCP/IP and UDP/IP protocols in your FPGA PGA Synthesisable 10/25/40/100 Gbit/s Ethernet PCS code for ultra-…
1.2 Gbps LVDS transmitter/receiver
The interface to the core logic in receiver mode includes the signal pins (out_p and out_n) to receive data and the control pins …
1 Gbps Rail to Rail LVDS receiver
065TSMC_LVDS_08 is LVDS receiver with rail to rail input range.
065TSMC_LVDS_07 is LVDS transmitter.
Programmable CMOS LVDS Transmitter/Receiver
LVDS device consists of one common bandgap reference voltage generator, a number of LVDS transmitter pad groups with their bias b…
16 Gbps APXpress PHY with 4-tap Tx FIR, CTLE, 12-tap DFE, and 30 dB IL target. Part of the Inova APXpress ecosystem
Die-to-Die / Short-Reach SerDes
32 Gbps UCIe-class links with CTLE and CTLE+DFE on GF Fotonix™, under development
The USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specific…
High Speed Inter-CHIP USB 2.0 PHY
USB is the ubiquitous peripherals interconnect of choice for a large number of computing and consumer applications.
The rapid proliferation of high-performance mobile and handheld devices has resulted in increasing requirements for non-volatile …
ONFI 3.2 NAND Flash PHY IP Compliant to JEDEC
The Open NAND Flash Interface (ONFI) is an Open standard for NAND Flash Memory chips.
The eMMC5.1 PHY is a fully compliant PHY layer for JEDEC eMMC5.1 and eMMC5.1 JESD84-B50 specification.
10G TBI (PCS) Ethernet Verification IP
The 10G TBI Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY layer interfaces of desi…
Open LVDS Display Interface (OpenLDI) Verification IP
Open LVDS Display Interface(OpenLDI) specification was developed through the cooperation of companies in the semiconductor, displ…
The SmartDV's LVDS verifies the Radio Front end-Baseband digital parallel interface.LVDS Verification IP can be used to verify BB…