Vendor: T2M GmbH Category: Single-Protocol PHY

Display Port 1.2 Tx PHY & Controller IP (Silicon Proven in STMicro 28FDSOI)

Our Display Port is VESA DP1.1a, DP1.2 and eDP compliant with four main lanes and an auxiliary channel The DP transmitter accepts…

Overview

Our Display Port is VESA DP1.1a, DP1.2 and eDP compliant with four main lanes and an auxiliary channel The DP transmitter acceptsDP1.1a HBR (2.7Gbps) and RBR (1.62Gbps) data rates; it can also support turbo mode (3.24Gbps) and HBRII (5.4Gbps) of DP1.2 standard. Signals are sampled from 1/2/4-lane double-wide DP stream data.

Key features

  • Display Port v1.2 Transmitter [1.62 - 2.7 - 5.4 Gbps/lane]
  • Embedded Display Port v1.4 Transmitter
  • HDMI v1.4 and Display Port v1.2 Combo receiver
  • DP SST and MST compliant
  • Support video format of RGB, YCbCr 4:4:4/4:2:2
  • Deep color up to 16bit per component, H Sync, V Sync, Field ID (Interlaced modes) and DE.
  • Support dual bus video
  • Audio up to 4ch I2S
  • Support HDCP 1.3
  • VESA DP1.1a, DP1.2a, eDP v1.3 and iDP v1.0 compliant
  • DP1.1a HBR (2.7Gbps), RBR (1.62Gbps) Turbo mode (3.24Gbps) and HBRII (5.4Gbps)
  • Support DP 1.2 side band and GTC messages
  • Support DP 1.2 3D and SDP nesting
  • To facilitate lower test cost and improve test coverage, a loopback test is provided to check for the functionality of the transmitter in different speed modes

Block Diagram

Benefits

  • Support 1, 2, or 4 lanes configuration, up to 5.4Gbps
  • Audio either I2S or parallel
  • 1MHz AUX channel
  • Support I2C (for MCCS & EDID) and Native over-AUX
  • Support UART over AUX

Applications

  • Setup Boxes
  • Smart TV
  • DP - HDMI Convertors

What’s Included?

  • Verilog RTL or netlist source code of LINK controller.
  • Abstracted timing models for synthesis and STA
  • Timing constrains for synthesis and physical layout
  • Behavioural Verilog Model, simulation test bench, run control scripts, and test stimuli
  • Physical design database
  • Integration guidelines
  • Reference software sample code

Specifications

Identity

Part Number
Display Port v1.2 Tx PHY & Controller IP
Vendor
T2M GmbH
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Germany

Learn more about Single-Protocol PHY IP core

Three Design Aspects you shouldn't miss while building an NB-IoT Protocol Stack

It is very important that the design aspects of the NB-IoT device protocol stack ensure low module cost and low energy consumption. This is required to match the industry expected module costs. This paper outlines some of the NB-IoT Protocol stack specification flexibilities and generic design aspects that are to be considered to meet the above requirements, especially with reference to LTE.

UFS Goes Mainstream

UniversalFlash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniPro as well as eMMC form factors to simplify adoption and development.

Design IP Faster: Introducing the C~ High-Level Language

In this paper, we introduce a new high-level, dataflow programming language called C~ (“C flow”) that further increases productivity by raising the level of abstraction from behavioral descriptions, while overcoming the limitations of C for hardware design. We present the syntax and semantics of this language, and the framework that provides hardware and software code generation. This paper illustrates the benefits of using C~ for hardware design of a IEEE 802.3 MAC, synthesized for FPGA and for 90nm CMOS technology.

Universal Flash Storage: Mobilize Your Data

Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

Can MIPI and MDDI Co-Exist?

Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

Frequently asked questions about Single-Protocol PHY IP

What is Display Port 1.2 Tx PHY & Controller IP (Silicon Proven in STMicro 28FDSOI)?

Display Port 1.2 Tx PHY & Controller IP (Silicon Proven in STMicro 28FDSOI) is a Single-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP