Vendor: Chevin Technology Limited Category: Single-Protocol PHY

10/25/40/100Gbit/s Ethernet PCS/PMA

Smooth integration of TCP/IP and UDP/IP protocols in your FPGA PGA Synthesisable 10/25/40/100 Gbit/s Ethernet PCS code for ultra-…

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Overview

Smooth integration of TCP/IP and UDP/IP protocols in your FPGA

PGA Synthesisable 10/25/40/100 Gbit/s Ethernet PCS code for ultra-low latency 10/25/40/100Gbit/s connectivity 1025GBASE-R

The 10/25/40/100G PCS IP block simplifies FPGA integration of an ultra-fast 10/25/40/100Gbit/s Ethernet PCS Layer in FPGA

IEEE802.3by specification for coding/decoding using 64b66b rules, scrambling with a powerful polynomial and gearbox

Proven on Alpha-Data ADM-PCIE-8V3 board to reduce PCS latency down to 42.3ns/99ns between XGMII and XSBI interfaces.

Key features

  • 10/25/40/100Gbit Ethernet Connectivity in Intel and AMD/Xilinx FPGAs
  • Designed to IEEE 802.3by specification
  • 10Gbit/s Low latency, 109 ns Round trip time, XGMII -> Wire -> XGMII
  • 2404 LUTs
  • 25Gbit/s Low latency, 99 ns Round trip time, XGMII -> Wire -> XGMII
  • 5250 LUTs
  • Integrated 64b66b codec, scrambler/descrambler and gearbox 66/32bit
  • Fault management
  • BER monitoring
  • PRBS pattern generator/checker
  • Statistics block
  • Options
    • Encrypted Netlist
    • XGMII Interface to MAC directly or via XAUI

Block Diagram

10/25/40/100Gbit/s Ethernet PCS/PMA block diagram

Benefits

  • The application side can be driven by any XGMII compatible MAC with a 64bit interface at 156.25MHz.The PHY manages link encoding and scrambling, while adapting the data rate to the reference clocks.
  • A detailed statistics block provides a running count of frames sent and received with individual 64bit counters for frames, BER events, illegal codes and decode errors, which can be monitored through the Host Interface
  • Reference design available for Alpha-Data ADM-PCIE-KU3 or AMD Xilinx KC705 development board using standard software development tools when integrated with higher layers from Chevin Technology’s portfolio of IP blocks.

Applications

  • Trade execution & monitoring
  • Data Storage & Capture systems
  • HPC / Big Data systems
  • Signal processing systems
  • Data Mining

What’s Included?

  • Encrypted netlist/ source code for UltraScale AND 7 Series FPGAs
  • Datasheet & User Guide to assist integration
  • Reference Design on Alpha-Data ADM-KU3 and Xilinx KC705 development board
  • Simulation Test bench
  • Build scripts for ISE/Vivado
  • Support for integration into FPGA

Specifications

Identity

Part Number
10/25/40/100Gbit/s Ethernet PCS/PMA
Vendor
Chevin Technology Limited
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Chevin Technology Limited
HQ: UK
Chevin Technology delivers high performance, configurable Ethernet IP Cores for Intel and AMD Xilinx FPGAs. Our goal is to provide reliable, hardware accelerator capabilities for high end FPGAs that are cost effective and straightforward to implement into client’s projects, using a minimum of FPGA resources. Our Ethernet IP cores are developed and comprehensively tested in-house, so we can offer valuable, expert knowledge and responsive engineering support to smooth the path for successful integration into client products. Chevin Technology’s IP Cores achieve high throughput and sustained data rates to maximise link utilization. The compact, ‘all logic’ architecture requires no CPU/SW, therefore reducing complexity, latency and energy consumption, while leaving maximum space for further design logic on customer FPGAs. Chevin Technology’s Ethernet IP Cores also feature our patented Silicon Software Solution, which provides further design flexibility and cost efficiency, as clients have the option of adding extra features as required throughout the design cycle. Client projects include international defence; medical research, scientific research, industrial imaging, data storage.
Contact Chevin Technology Limited

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Frequently asked questions about Single-Protocol PHY IP

What is 10/25/40/100Gbit/s Ethernet PCS/PMA?

10/25/40/100Gbit/s Ethernet PCS/PMA is a Single-Protocol PHY IP core from Chevin Technology Limited listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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