Die-to-Die / Short-Reach SerDes
32 Gbps UCIe-class links with CTLE and CTLE+DFE on GF Fotonix™, under development
Overview
Short-reach SerDes IP for chiplet-to-chiplet connectivity on monolithic electro-photonic platforms. Under development. Complementary WDM photonics IP also in progress for complete electro-photonic chiplet solutions for the AI era.
Key features
- 32 Gbps data rate
- CTLE and CTLE+DFE variants
- GF Fotonix™ platform
- Under development
Applications
- Chiplet interconnect
- UCIe-class links
- Co-packaged optics
- AI accelerator fabrics
What’s Included?
- GDS layout database
- Liberty timing models (.lib)
- LEF layout exchange format
- Documentation available
- Integration support package
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about Single-Protocol PHY IP core
Inova Semiconductors and StarIC Announce Initial Silicon Validation, Accelerating APXpress Ecosystem for Physical AI
StarIC opens design center in The Netherlands
StarIC and GlobalFoundries announce strategic partnership, release high-Speed TIA and drivers to advance silicon photonics ecosystem
StarIC appoints Redtree Solutions as Sales Representative in Pan-Europe
Frequently asked questions about Single-Protocol PHY IP
What is Die-to-Die / Short-Reach SerDes?
Die-to-Die / Short-Reach SerDes is a Single-Protocol PHY IP core from StarIC Inc listed on Semi IP Hub.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.