Vendor: StarIC Inc Category: Single-Protocol PHY

APX PHY for Physical AI

16 Gbps APXpress PHY with 4-tap Tx FIR, CTLE, 12-tap DFE, and 30 dB IL target. Part of the Inova APXpress ecosystem

PHY GlobalFoundries 22nm FDX Silicon Proven View all specifications

Overview

16 Gbps asymmetric full-duplex PHY for Inova APXpress, built on StarIC's long-reach SerDes (4-tap Tx FIR, CTLE, 12-tap DFE, ~30 dB IL target). For zonal automotive, robotics, and Physical AI platforms that need deterministic, time-synchronized links.

Validated with Inova on GlobalFoundries 22FDX®. APXpress system-level specs include up to 500 virtual channels at 16 Gbps; this IP is StarIC's PHY contribution to that program.

Available as part of StarIC's platform offering for partners building within the Inova APXpress ecosystem, including reference architectures such as the MIPS–Inova–GlobalFoundries Physical AI robotics control platform.

Process: GlobalFoundries 22FDX® (validated); portable architecture

Key features

  • 16 Gbps data rate (APXpress physical layer)
  • 4-tap Tx FIR, CTLE, 12-tap DFE
  • Targeting 30 dB insertion loss
  • Asymmetric full-duplex
  • Deterministic, low-latency connectivity for zonal architectures
  • Up to 500 virtual channels (APXpress system-level)
  • Silicon validated with Inova on GF 22FDX®

Applications

  • Physical AI and robotics
  • Multi-axis motion control
  • Zonal automotive architectures
  • Mixed-criticality edge platforms

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 22nm FDX Silicon Proven

Specifications

Identity

Part Number
apx-phy-physical-ai
Vendor
StarIC Inc
Type
Silicon IP
Controller / PHY
PHY

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Canada

Learn more about Single-Protocol PHY IP core

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Frequently asked questions about Single-Protocol PHY IP

What is APX PHY for Physical AI?

APX PHY for Physical AI is a Single-Protocol PHY IP core from StarIC Inc listed on Semi IP Hub. It is listed with support for globalfoundries Silicon Proven.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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