Vendor: Arasan Chip Systems Inc. Category: Single-Protocol PHY

ONFI 3.2 NAND Flash PHY IP Compliant to JEDEC

The Open NAND Flash Interface (ONFI) is an Open standard for NAND Flash Memory chips.

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Overview

The Open NAND Flash Interface (ONFI) is an Open standard for NAND Flash Memory chips. ONFI seeks to standardize the low-level interface. ONFI 3.2 is the standard for a High-Speed NAND Flash interface. It has multiple modes of operation like SDR, NV-DDR and NV-DDR2 modes. Micron’s Clear NAND operations such as Queue page read and Program page pause, Program page resume, Program page delay are also supported. ONFI 3.2 PHY extends the benefits of ONFI 3.x and 2.3 standards. It provides a high-speed interface supporting transfer rates up to 400 MT/s. It also supports the EZ-NAND interface. Lots of performance-enhancing features like Interleaving operations, Multi-plane operations is supported. ONFI 3.2 PHY incorporates the full TX/RX logic for NV-DDR2/NV-DDR mode of operation and is backward compatible to the SDR mode of operation. ONFI 3.2 improves on version ONFI 3.0 with more robust power sequencing to protect NAND flash, more flexible timing to support NAND usage in different topologies, improved parameters for testing, and other enhancements. Included in the OFNI 3.2 PHY is a set of high-speed I/O pads compatible to ONFI 1.8v 266 MHz NV-DDR2 and 3v 100 MHz NV-DDR.

Key features

  • Compliant to ONFI revision 3.2 standard
  • Silicon proven PLL to support all frequencies from 10MHz to 266MHz, and DLL to improve data sampling accuracy dynamically
  • Include ONFI 3.2 I/O pads compatible to 1.8v NV-DDR2 533 MT/s and 3v NV-DDR 200 MT/s
  • Supports NV-DDR2 mode of operation supporting up to 266MHz
  • Supports NV-DDR mode of operation supporting up to 100MHz
  • Supports legacy Asynchronous devices operating from 10MHz to 50MHz
  • Can be used with any other ONFI digital controller
  • Supports differential signaling of DQS and RE signals
  • Supports four levels of drive strength as mentioned in the ONFI 3.2 standard

Block Diagram

ONFI 3.2 NAND FLASH PHY IP Compliant to JEDEC block diagram

Benefits

  • Integrated solution including silicon proven PHY and I/O pads supporting 533 MT/s

What’s Included?

  • GDS-II Database
  • LVS Netlist
  • Physical Abstract Models (LEF)
  • Timing Models (LIB)
  • Process Specific Integration Guide

Specifications

Identity

Part Number
ONFI 3.2 NAND FLASH PHY IP Compliant to JEDEC
Vendor
Arasan Chip Systems Inc.
Type
Silicon IP

Files

Product Sheet Download

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Provider

Contact Arasan Chip Systems Inc.

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Frequently asked questions about Single-Protocol PHY IP

What is ONFI 3.2 NAND Flash PHY IP Compliant to JEDEC?

ONFI 3.2 NAND Flash PHY IP Compliant to JEDEC is a Single-Protocol PHY IP core from Arasan Chip Systems Inc. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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