Arasan to demonstrate the industry's first MIPI SWI3S™ IP at the MIPI Member meet in Taipei
Arasan provides a Total SWI3S™ IP Solution including the SWI3S™ PHY which will be available on multiple foundry nodes 22nm and below.
Vendor:
Arasan Chip Systems Inc.
Category:
Single-Protocol PHY
eMMC 5.1 HS400 PHY
The eMMC5.1 PHY is a fully compliant PHY layer for JEDEC eMMC5.1 and eMMC5.1 JESD84-B50 specification.
Overview
The eMMC5.1 PHY is a fully compliant PHY layer for JEDEC eMMC5.1 and eMMC5.1 JESD84-B50 specification. It is backward compatible with eMMC4.51 and earlier versions of the specifications. This allows the designers of the SoC to easily support the eMMC interface and optimize the performance and power while maintaining interoperability with eMMC 5.0 and eMMC 5.1 devices.
eMMC 5.1 HS400 PHY IP consists of hardened PHY IP and RTL block code. The hard-macro consists of analog IPs, such as eMMC 5.1 interface Pads, Impedance Calibration Pad, an analog DLL, and the DLL wrapper. The RTL Block code includes the Host/Device controller.
To assist with eMMC 5.1 IP integration, the vendor provides all of the back-end views of eMMC 5.1 GPIO Pads and CALIO Pad integrated with TSMC ESD protection structure for I/O VDDQ, VSSQ, and Power Clamps.
Key features
- Suitable for Transmitter, Receiver, and Data Strobe pins
- I/O voltage: 1.8V or 3.3V
- Core voltage: 0.9V
Block Diagram
eMMC 5.1 HS400 PHY block diagram
Benefits
- Silicon proven, fully compliant core
- Premier direct support from Arasan IP core designers
- Easy-to-use industry standard test environment
- Unencrypted source code allows easy implementation
- Reuse Methodology Manual guidelines (RMM) compliant verilog code
What’s Included?
- GDSII database
- LVS Netlist
- Physical Abstract Model (LEF)
- Timing Models
- Behavioral Models
- Design Integration Guide
- Technical Documentation
Specifications
Identity
Part Number
eMMC 5.1 HS400 PHY
Vendor
Arasan Chip Systems Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about Single-Protocol PHY IP
What is eMMC 5.1 HS400 PHY?
eMMC 5.1 HS400 PHY is a Single-Protocol PHY IP core from Arasan Chip Systems Inc. listed on Semi IP Hub.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.