Vendor: SmartDV Category: Single-Protocol PHY

LVDS Verification IP

The SmartDV's LVDS verifies the Radio Front end-Baseband digital parallel interface.LVDS Verification IP can be used to verify BB…

Verification IP View all specifications

Overview

The SmartDV's LVDS verifies the Radio Front end-Baseband digital parallel interface.LVDS Verification IP can be used to verify BBIC or RFIC and SPI Master or Slave following the LVDS basic protocol as defined in LVDS and provides the following features.

LVDS Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

LVDS Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Follows LVDS Atmel-42415-WIRELESS-AT86RF215_Datasheet specification.
  • Supports BBIC and RFIC Mode.
  • Supports half duplex data transfer.
  • Supports both data path transaction and SPI control interface transactions.
  • Supports following IQ data path transaction
    • Supports TXD, RXD09 and RXD24.
    • Supports 2bit I SYNC and Q SYNC data.
    • Supports 14bit I data and Q data
    • Support error injection
  • Supports following SPI control interface transaction
    • 2bit command plus 14bit address and 8bit data control field format
    • plane power consumption to negligible levels
    • Support Master and Slave Mode
    • Support baud rate selection
    • Support single and burst transfer mode
  • Supports various kinds of errors as follows
    • I SYNC error
    • Q SYNC error
    • Invalid zero word error
    • Illegal write data error
    • Read only address error
  • Status counters for various events on bus.
  • Built in functional coverage analysis.
  • Callbacks in BBIC and RFIC for various events.
  • Functional coverage to cover each and every feature of the LVDS specification.
  • Test suite to test each and every feature of LVDS specification.

Block Diagram

LVDS VIP block diagram

Benefits

  • Faster test bench development and more complete verification of LVDS designs.
  • Simplifies results analysis.
  • Runs in every major simulation environment.
  • Easy to use command interface simplifies testbench control and configuration of BBIC and RFIC.
  • Comes with complete test suite to test each and every feature of LVDS.

What’s Included?

  • Complete regression suite containing all the LVDS testcases.
  • Examples showing how to connect various components,and usage of BBIC,RFIC and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation contains User's Guide and Release notes.

Specifications

Identity

Part Number
LVDS VIP
Vendor
SmartDV
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about Single-Protocol PHY IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about Single-Protocol PHY IP

What is LVDS Verification IP?

LVDS Verification IP is a Single-Protocol PHY IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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