Vendor: Arasan Chip Systems Inc. Category: Single-Protocol PHY

High Speed Inter-CHIP USB 2.0 PHY

USB is the ubiquitous peripherals interconnect of choice for a large number of computing and consumer applications.

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USB 2.0 View all specifications

Overview

USB is the ubiquitous peripherals interconnect of choice for a large number of computing and consumer applications. Many systems provide a comprehensive set of drivers to support all commonly available USB peripherals. This enables consumers to purchase and use USB peripherals without having to install a new driver, thus strengthening the popularity of USB. In addition, Arasan supplies USB silicon, so costs are normally very low for product manufacturing of USB hosts and peripherals.

It is becoming increasingly attractive to use USB as a chip-to-chip interconnect within a product (without the use of external cables and connectors). However, because USB was designed to enable hot-plugging of peripherals over cables up to 5 meters in length, there are certain power and implementation issues that are not attractive for many chip-to-chip interconnect solutions.

 

USB 2.0 HSIC PHY

To better meet the needs of a USB chip-to-chip interconnect, HSIC removes the analog transceivers, thus reducing complexity, cost and manufacturing risk.

USB 2.0 HSIC PHY is a 2-signal (strobe, data) source-synchronous serial interface which uses 240Mhz DDR signaling to provide High-Speed 480Mps USB transfers which are 100% host driver compatible with traditional USB cable-connected topologies. Full-Speed (FS) and Low-Speed (LS) USB transfers are not directly supported by the HSIC interface (an HSIC enabled hub can provide FS and LS support, as well as IC_USB support).

Arasan is the among the industry’s first providers of USB IP with the launch of its USB 1.1 Device IP in 1996 and the industries ONLY provider to offer a Total USB 2.0 IP Solution which includes its USB 2.0 Host IP Core, USB 2.0 Device IP Core, USB 2.0 Hub IP, USB 2.0 OTG IP, the USB 2.0 PHY IP and software for multiple OS.

Key features

  • High-Speed 480Mbps data rate only
  • Source-synchronous serial interface
  • No power consumed unless a transfer is in progress.
  • Maximum trace length of 10cm
  • No hot Plug-n-Play support, no hot removal/attach
  • Signals driven at 1.2V standard LVCMOS levels
  • Designed for low-power applications
  • No high-speed chirp protocol, the HSIC interface is always operated at high-speed
  • HSIC host or peripheral can be powered in any order

Block Diagram

High Speed Inter-CHIP USB 2.0 PHY block diagram

Benefits

  • Silicon proven
  • Performance and Power efficient interface
  • Leverages USB infrastructure

What’s Included?

  • GDS-II
  • CDL netlist for LVS
  • DRC and Antenna reports
  • LIB files
  • Userguide and Integration Guides
  • LEF
  • Scan-inserted netlist for DFT
  • Verification Environment with behavioral models

Specifications

Identity

Part Number
High Speed Inter-CHIP USB 2.0 PHY
Vendor
Arasan Chip Systems Inc.
Type
Silicon IP

Standards & Interfaces

Supported Standards
USB 2.0

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Arasan Chip Systems Inc.

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Frequently asked questions about Single-Protocol PHY IP

What is High Speed Inter-CHIP USB 2.0 PHY?

High Speed Inter-CHIP USB 2.0 PHY is a Single-Protocol PHY IP core from Arasan Chip Systems Inc. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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