LVDS Synthesizable Transactor provides a smart way to verify the LVDS component of a SOC or a ASIC in Emulator or FPGA platform.
- Single-Protocol PHY
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
LVDS Synthesizable Transactor provides a smart way to verify the LVDS component of a SOC or a ASIC in Emulator or FPGA platform.
The LVDS Verification IP provides an effective & efficient way to verify the LPC components of an IP or SoC.
USB-C 3.1/DP TX PHY for TSMC 6FF, North/South Poly Orientation
The USB-C 3.1/DisplayPort Tx 1.3 Tx IP solution consists of USB-C 3.1/DisplayPort 1.3 PHYs, USB-C 3.1/DisplayPort 1.3 controllers…
USB 3.1 DisplayPort PHY - TSMC 10FF, North/South Poly Orientation
The USB-C 3.1/DisplayPort Tx 1.3 Tx IP solution consists of USB-C 3.1/DisplayPort 1.3 PHYs, USB-C 3.1/DisplayPort 1.3 controllers…
USB-C 3.1/DP TX PHY for GF 22FD-SOI, North/South Poly Orientation
The USB-C 3.1/DisplayPort Tx 1.3 Tx IP solution consists of USB-C 3.1/DisplayPort 1.3 PHYs, USB-C 3.1/DisplayPort 1.3 controllers…
GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in SAM 14LPP
The GPHY is a fully integrated IP Core with low power consumption for Giga 10/100/1000 Ethernet applications.
The LVDS implements LVDS TIA/EIA protocol, providing a low-voltage, high-speed point-to-point signal interface.
Low-power, long-reach, multi-protocol PHY for PCIe 4.0
The first IP for PCIe 3.1 with L1 sub-states support
USB 2.0 PHY IP, Silicon Proven in TSMC 16FFC
The entire physical layer (PHY) IP solution for USB 2.0 was created to provide exceptional performance and consume little power.
USB 3.1 Type-C PHY IP, Silicon Proven in SMIC 55LL
The USB3.1Type-C PHY is a high-speed, SERDES IP with high performance that was created for semiconductors that allow high-bandwid…
USB 2.0 PHY IP, Silicon Proven in TSMC 90G
The USB2.0 PHY IP is a full physical layer (PHY) IP solution created for exceptional performance and low power consumption.
USB 2.0 PHY IP, Silicon Proven in TSMC 65LP
A physical layer (PHY) IP solution designed for outstanding performance and minimal power consumption is the USB2.0 PHY IP.
USB 2.0 PHY IP, Silicon Proven in TSMC 55LP
In order to deliver great performance and use little power, the whole physical layer (PHY) IP solution for USB 2.0 was developed.
USB 2.0 PHY IP, Silicon Proven in TSMC 12FFC
The whole physical layer (PHY) IP solution for USB 2.0 was designed for outstanding performance and low power consumption.
USB 2.0 PHY IP, Silicon Proven in TSMC 7FF
The USB2.0 PHY IP is a full physical layer (PHY) IP solution created for exceptional performance and low power consumption.
USB 3.0 PHY IP, Silicon Proven in TSMC 55LP
For auxiliary devices, a Universal Serial Bus (USB) transceiver is offered.
USB 3.0 PHY IP, Silicon Proven in TSMC 40LP
A Universal Serial Bus (USB) transceiver is available for auxiliary devices.
USB 3.0 PHY IP, Silicon Proven in TSMC 22ULP
The USB 3.0 PHY IP Core is a transceiver provided for supplementary devices, compliant with UTMI (USB SuperSpeed), USB 3.0, and U…
USB 3.0 PHY IP, Silicon Proven in TSMC 16FFC
A Universal Serial Bus (USB) transceiver is available for auxiliary devices.