USB 2.0 PHY IP, Silicon Proven in UMC 55SP/EF
The USB2.0 PHY IP is a physical layer (PHY) IP solution created for exceptional performance and low power consumption.
- USB 2.0
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
USB 2.0 PHY IP, Silicon Proven in UMC 55SP/EF
The USB2.0 PHY IP is a physical layer (PHY) IP solution created for exceptional performance and low power consumption.
USB 2.0 PHY IP, Silicon Proven in TSMC 40LP/LL
The USB2.0 PHY IP is an entire physical layer (PHY) IP solution built for high performance and low power consumption.
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 40LP
This Display Port v1.4 Rx PHY IP Core supports Channel capacity, offering programmable analog characteristics like CDR Bandwidth,…
USB 3.0 PHY IP, Silicon Proven in TSMC 28HPC+
A Universal Serial Bus (USB) transceiver which is provided for peripheral devices.
SD4.1 UHS-II IP utilizes distinctive SerDes technology to attain a speed of 312MB/s for UHS-II while maintaining low power consum…
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 28HPC
The capacity of the Display Port 1.4 Rx IP Channel is supported.
USB 2.0 PHY IP, Silicon Proven in TSMC 28HPC+
The USB2.0 PHY IP is an entire physical layer (PHY) IP solution built for high performance and low power consumption.
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR B…
GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in UMC 28HPC
The GPHY is a fully integrated single chip for Gigabit Ethernet applications with lowest power consumption.
Rail to rail LVDS receiver 1 Gbps
LVDS_RX is LVDS receiver with rail to rail input range.
The interface to the core logic includes signal pin (INP) to transmit data and control pin ( EN) to configure the state of the tr…
LVDS-based IOs The Bi-directional LVDS is in production from 90nm CMOS to 16/12nm FinFET and taped out in 7nm FinFET.
Video LVDS SerDes Transmitter-Receiver IP Core
The Video LVDS SerDes Transmitter / Receiver IP Core provides a , easy-to-use Serializer/Deserializer (SerDes) solution to interf…
The TRC5024CPA is a four lane Gen 1 and 2 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transmi…
Clock and Data Recovery of HDB3/B3ZS coded signals
An all-digital solution suitable for clock/data recovery of HDB3/B3ZS coded signals.
32 Gbps PCIe-class links, 4-tap Tx FIR, CTLE, 12-tap DFE, 30 dB IL target
USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
The USB4 PHY IP provides designers with the industry's best combination of small area and low power with support for the process …
USB4 PHY - TSMC N4P 1.2V, North/South Poly Orientation
The USB4 PHY IP provides designers with the industry's best combination of small area and low power with support for the process …
USB4 PHY - TSMC N3E 1.2V, North/South Poly Orientation
The USB4 PHY IP provides designers with the industry's best combination of small area and low power with support for the process …
USB4 PHY - TSMC N3P 1.2V, North/South Poly Orientation
The USB4 PHY IP provides designers with the industry's best combination of small area and low power with support for the process …