The LVDS Receiver converts up to 10 pairs of LVDS data streams into 70-bit of CMOS data and then feeds the data to the logic core…
- IBM
- 65nm
- LPe
- Silicon Proven
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
The LVDS Receiver converts up to 10 pairs of LVDS data streams into 70-bit of CMOS data and then feeds the data to the logic core…
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…
The LVDS transceiver IP is a Serializer/Deserializer (SERDES) pair that transparently translates 12–bit parallel bus into serial …
The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial…
The LVDS transmitter converts 28-bit data into 4-pair LVDS data stream.
The LVDS Receiver IP is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…
The USB11PHY is an IP version of USB transceiver.
The USB11PHY is an IP version of USB transceiver.
The USB1.1 PHY is an IP version of USB transceiver.
SMIC 0.18um Reduced Swing Differential Signaling Transmitter
This is an embedded bus transmitter for RSDS™ (Reduced Swing Differential Signaling) interface.
650M LVDS transmitter, 5 channel
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…
LVDS receiver, 650M, 5 channel
The LVDS Receiver IP is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…
The USB11PHY is an IP version of USB transceiver.
32:1 serializer followed by sub-LVDS drivers
The CCP2 transmitter consists of a 32:1 serializer followed by LVDS drivers for transmitting clock (or strobe) and data.
Sub-LVDS receiver followed by 1:4 de-serializer
The S13V25_CCP2RX _01 recovers a serial bit stream containing image data and converts it to a 4-bit 1/4 rate word.
SGMII IP Phy is Serial Giga bit Media Independent Interface (SGMII) IP core and provides a single lane 1.25Gbps date rate interfa…
The Lattice SGMII and Gb Ethernet PCS IP core implements the PCS functions of both the Cisco SGMII and the IEEE 802.3z (1000BaseX…
USB 2.0 Host/Device Transceiver With On-The-Go (OTG)
USB 2.0 HOST/DEVICE/OTG Transceiver is a fully integrated PHY Core which is a super-set of HOST and DEVICE PHY with High Speed (H…
USB 2.0 HOST Transceiver is a fully integrated PHY Core which is a super-set of HOST PHY with High Speed (HS), Full-Speed (FS) an…
USB 2.0 DEVICE Transceiver is a fully integrated PHY Core which is a super-set of DEVICE PHY with High Speed (HS), Full-Speed (FS…