Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: Single-Protocol PHY

32:1 serializer followed by sub-LVDS drivers

The CCP2 transmitter consists of a 32:1 serializer followed by LVDS drivers for transmitting clock (or strobe) and data.

SMIC 130nm G View all specifications

Overview

The CCP2 transmitter consists of a 32:1 serializer followed by LVDS drivers for transmitting clock (or strobe) and data. The LVDS drivers operate in subLVDS mode only, which is defined in the CCP2 standard. Each LVDS driver has a programmable on-die termination resistor to facilitate high frequency operation, and supports test data output mode. The LSB of 32-bit data is sent first. The clock for the serializer is generated using a local PLL. The maximum data rate for the transmitter is 960Mb/s.

Key features

  • High speed subLVDS data/clock or data/strobe signaling
  • Internal PLL for high speed clock generation
  • Programmable on-die termination resistors
  • Power down mode
  • Built-in test pattern generation
  • Full industrial operating temperature range -40 ~ +125°
  • SMIC 0.13um Logic Salicide Process (1P6M, 1.2V/2.5V)

Silicon Options

Foundry Node Process Maturity
SMIC 130nm G —

Specifications

Identity

Part Number
S13V25_CCP2TX_01
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP

Provider

Learn more about Single-Protocol PHY IP core

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Frequently asked questions about Single-Protocol PHY IP

What is 32:1 serializer followed by sub-LVDS drivers?

32:1 serializer followed by sub-LVDS drivers is a Single-Protocol PHY IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for smic.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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