Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: Single-Protocol PHY

Sub-LVDS receiver followed by 1:4 de-serializer

The S13V25_CCP2RX _01 recovers a serial bit stream containing image data and converts it to a 4-bit 1/4 rate word.

SMIC 130nm G View all specifications

Overview

The S13V25_CCP2RX _01 recovers a serial bit stream containing image data and converts it to a 4-bit 1/4 rate word. The receiver defined in this IP is only required to interface with the image sensor. The receiver consists of two LVDS receiver cells (Strobe and Data) followed by a 1:4 de-serializer. Only Data-Strobe mode needs to be supported in this design. Therefore the clock may always be recovered using a DDR Flop clocked by the XOR of Strobe and Data. In addition, only Sub-LVDS electrical requirements must be met.

Key features

  • Sub-low voltage differential signaling input: VID = 25mV MIN.
  • Converts the subLVDS strobe/data (up to 960 Mbps throughput bandwidth) back into parallel 4 bits of CMOS data/strobe
  • Power-down control function
  • Full industrial operating temperature range -40 ~ +125 °C
  • SMIC 0.13um Logic Salicide Process (1p6m, 1.2V/2.5V)
  • On chip 100ohm resistance between receivers’ each positive input and negative input
  • Positive clock edge with data output

Silicon Options

Foundry Node Process Maturity
SMIC 130nm G —

Specifications

Identity

Part Number
S13V25_CCP2RX _01
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP

Provider

Learn more about Single-Protocol PHY IP core

VeriSilicon Launches GCNanoOptimaV, a Next-Generation 2.5D GPU IP for Wearables

Featuring dedicated hardware acceleration engines and an optimized memory architecture, GCNanoOptimaV significantly enhances graphics rendering performance and memory efficiency, enabling richer and more responsive graphical user interfaces (GUIs) while addressing the stringent resource constraints of wearable applications.

Frequently asked questions about Single-Protocol PHY IP

What is Sub-LVDS receiver followed by 1:4 de-serializer?

Sub-LVDS receiver followed by 1:4 de-serializer is a Single-Protocol PHY IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for smic.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP