Overview
USB 2.0 HOST/DEVICE/OTG Transceiver is a fully integrated PHY Core which is a super-set of HOST and DEVICE PHY with High Speed (HS), Full-Speed (FS) and Low-Speed Transceivers integrated with On-The-Go Functionality and is compliant with the USB 2.0 Specification and latest Revision of the On The-Go and UTMI+ Specifications (UTMI+ Version 1.0 Level 3). It includes Data Pulsing, VBUS Pulsing, VBUS Comparators for Session Detection to support HNP (Host Negotiation Protocol) and SRP (Session Request Protocol), Clock/Data Recovery, on-chip PLL, Integrated & Calibrated Termination and Pull Up/Down Resistors with full Analog Transceiver functionality for the Complete USB 2.0 PHY as illustrated in the figure.
USB2 Host/Device/OTG transceiver has standard UTMI with SIE so that ASIC vendors are isolated from the high speed and analog circuitry associated with the transceiver, thus reducing the design risk and fastening the design cycle.
The core’s main blocks are clock/data recovery for FS/HS, PLL, transceiver state machines, data encoder/decoder and high-speed analog transceiver as can be seen in the main block diagram above.
Learn more about Single-Protocol PHY IP core
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Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.
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