Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: Single-Protocol PHY

SMIC 0.18um LVDS Transceiver

The LVDS transceiver IP is a Serializer/Deserializer (SERDES) pair that transparently translates 12–bit parallel bus into serial …

Contact Provider Request Datasheet
SMIC 180nm G View all specifications

Overview

The LVDS transceiver IP is a Serializer/Deserializer (SERDES) pair that transparently translates 12–bit parallel bus into serial stream. This single serial stream simplifies the transfer of 12-bit or less bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. In addition, this SERDES pair has built-in system and device test capability. The line loop back feature enables a user to check the integrity of the serial data transmission path of the transmitter and receiver while deserializing the serial data to parallel data at the receiver output. The local loop-back feature enables a user to check the integrity of the transceiver from the local parallel-bus side.

Key features

  • 30~60MHz 12:1/1:12 Serializer /Deserializer (720Mbps throughput)
  • Wide reference clock frequency tolerance: +/-500ppm
  • Internal PLL, no external PLL components are required
  • >2.0kV HBM ESD
  • Deserializer equalization up to 16dB boost at 720Mbps
  • Full industrial operating temperature range: -40 ~ +125 °C
  • SMIC 0.18um Logic Salicide Process (1p6m, 1.8V/3.3V)
  • Programmable pre-emphasis (0dB / 3dB / 6dB / 9dB)
  • Compatible with the TIA/EIA-644-A LVDS standard

Silicon Options

Foundry Node Process Maturity
SMIC 180nm G —

Specifications

Identity

Part Number
SMIC18_LVDS_04
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP

Provider

Contact VeriSilicon Microelectronics (Shanghai) Co., Ltd.

Learn more about Single-Protocol PHY IP core

UFS Goes Mainstream

UniversalFlash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniPro as well as eMMC form factors to simplify adoption and development.

Design IP Faster: Introducing the C~ High-Level Language

In this paper, we introduce a new high-level, dataflow programming language called C~ (“C flow”) that further increases productivity by raising the level of abstraction from behavioral descriptions, while overcoming the limitations of C for hardware design. We present the syntax and semantics of this language, and the framework that provides hardware and software code generation. This paper illustrates the benefits of using C~ for hardware design of a IEEE 802.3 MAC, synthesized for FPGA and for 90nm CMOS technology.

Universal Flash Storage: Mobilize Your Data

Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

Can MIPI and MDDI Co-Exist?

Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

Frequently asked questions about Single-Protocol PHY IP

What is SMIC 0.18um LVDS Transceiver?

SMIC 0.18um LVDS Transceiver is a Single-Protocol PHY IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for smic.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP