Serial GMII 1.25 Gbps Phy
SGMII IP Phy is Serial Giga bit Media Independent Interface (SGMII) IP core and provides a single lane 1.25Gbps date rate interfa…
Overview
SGMII IP Phy is Serial Giga bit Media Independent Interface (SGMII) IP core and provides a single lane 1.25Gbps date rate interface to MAC layer and consists of Physical Convergent Sublayer (PCS) and Physical Media Dependent (PMD). SGMII IP transmitter includes Rate-Adaptation, Transmit state-machine and Serializer and transmitter IO blocks. The Receiver consists of Sampler, Clock Data Recovery (CDR) and high performance Phase-Lock Loop (PLL), Synchronization, Receive state-machine, and Rate adaptation blocks. The SGMII IP has a high performance rate Auto-negotiation block to negotiate rates between transmitter and receiver. The SGMII core is an ideal solution for applications requiring to connect the ASIC/SoC MAC to external 1000 BaseT Phy, where lowest power and pin counts is needed.
Key features
- Supports Cisco Ver. 1.7 Serial-GMII specification
- Single 1.0 V core supply
- Supports GMII transfers
- Jitter Generation below 0.2 UI, Jitter tolerance (CDR) exceed 0.72 IU
- 1.25 Gbps Serial GMII interface
- LVDS IO
- At speed BIST SerDes Core
- 1149.1 compatible JTAG port, and clause 22/45 MDIO interface
Specifications
Identity
Files
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Provider
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Frequently asked questions about Single-Protocol PHY IP
What is Serial GMII 1.25 Gbps Phy?
Serial GMII 1.25 Gbps Phy is a Single-Protocol PHY IP core from TaraCom Integrated Products, Inc. listed on Semi IP Hub.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.