Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: Single-Protocol PHY

SMIC 0.13um LVDS Receiver

The LVDS Receiver IP is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…

SMIC 130nm LV View all specifications

Overview

The LVDS Receiver IP is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution and Dual Link transmission between Host and Flat Panel Display with up to UXGA resolution. It converts the LVDS data stream back into 70 bits of CMOS/TTL data with a variety of LCD panel controllers.

Key features

  • Function compatible with the National DS90CF386
  • Converts 4-pair LVDS data stream into parallel 28 bits of CMOS/TTL data
  • Converts 8-pair LVDS data stream into parallel 56 bits of CMOS/TTL data with double channel
  • Wide dot clock range: 25 ~ 170MHz, suitable for VGA, SVGA, XGA, SXGA, SXGA+ and UXGA
  • Supports Dual Link up to 170MHz dot clock for UXGA
  • On-chip DLL does not require any external component
  • Low-power CMOS design
  • Power-down control function
  • Compatible with the TIA/EIA-644 LVDS standards
  • Full industrial operating temperature range: -40 ~ +85 ¡ãC
  • SMIC 0.13um Logic Salicide Process (1p8m, 1.2V/3.3V)
  • Off chip 100ohm resistance between the receiver¡¯s positive input and negative input
  • Negative clock edge for data output
  • More detail, please go to below website to contact VeriSilicon location sales:http://www.verisilicon.com/cn/contactus.asp

Silicon Options

Foundry Node Process Maturity
SMIC 130nm LV —

Specifications

Identity

Part Number
S13V33_LVDSRX_03
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP

Provider

Learn more about Single-Protocol PHY IP core

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Frequently asked questions about Single-Protocol PHY IP

What is SMIC 0.13um LVDS Receiver?

SMIC 0.13um LVDS Receiver is a Single-Protocol PHY IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for smic.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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