USB 2.0 On-The-Go PHY; UMC 28nm HLP Process
USB 2.0 On-The-Go PHY; UMC 28nm HLP Process
- USB 2.0
- UMC
- 28nm
- HLP
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
USB 2.0 On-The-Go PHY; UMC 28nm HLP Process
USB 2.0 On-The-Go PHY; UMC 28nm HLP Process
USB2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process_x005F_x000D_ cost down from FZOTG266HJ0C_A
USB2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process cost down from FZOTG266HJ0C_A
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic e-Flash Process
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic e-Flash Process
Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process.
Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process.
SMIC 28nm USB3.0 Dual Role PHY/Type-C
The USB3.0 Type-C PHY IP is designed to the USB 3.0, USB2.0 Specification and the USB Type-CTM USB Cable and Connector Specificat…
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…
28nm HPC+ USB3.1 gen2 PHY(10Gbps)
28nm HPC+ USB3.1 gen2 PHY(10Gbps)
28nm HPC USB3.1 gen2 PHY(10Gbps)
28nm HPC USB3.1 gen2 PHY(10Gbps)
USB 3.0 PHY; UMC 28nm HPC_Plus +RVT+LVT Logic Process
USB 3.0 PHY; UMC 28nm HPC_Plus +RVT+LVT Logic Process
USB 2.0 On-The-Go PHY; UMC 40nm Logic LP/RVT Low-K Process
USB 2.0 On-The-Go PHY; UMC 40nm Logic LP/RVT Low-K Process
USB 2.0 On-The-Go PHY; UMC 28nm HPC+ RVT Logic Process
USB 2.0 On-The-Go PHY; UMC 28nm HPC+ RVT Logic Process
USB2.0 OTG PHY UMC 40nm LP/RVT process, for Flip chip Bump type_LF
USB2.0 OTG PHY UMC 40nm LP/RVT process, for Flip chip Bump type_LF
USB 2.0 On-The-Go PHY, analog part ; UMC 28nm HPC RVT Logic Process
USB 2.0 On-The-Go PHY, analog part ; UMC 28nm HPC RVT Logic Process
PCIE Gen.II PHY; UMC 65nm LP/RVT LowK Logic Process.
PCIE Gen.II PHY; UMC 65nm LP/RVT LowK Logic Process.
ONFI PHY Compensation Block for ONFI4.0 application; UMC 40nm LP/RVT Logic Process
ONFI PHY Compensation Block for ONFI4.0 application; UMC 40nm LP/RVT Logic Process
1.8V Sub-LVDS Receiver 650Mbps; UMC 28nm HPC process
1.8V Sub-LVDS Receiver 650Mbps; UMC 28nm HPC process
LVDS Transmitter 700Mbps; UMC 28nm HPC Process
LVDS Transmitter 700Mbps; UMC 28nm HPC Process
2.5V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process. (Modify layout )
2.5V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process.
3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC plus proces
3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC plus proces
The bias block only for FXLVDSRX080HH0L, UMC 40nm LP/RVT LowK Logic Process
The bias block only for FXLVDSRX080HH0L, UMC 40nm LP/RVT LowK Logic Process