Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
Two Port OTG USB2.0 PHY;BOAC version; Wire bonding;UMC 40 nm LP/RVT process.
Two Port OTG USB2.0 PHY;BOAC version; Wire bonding;UMC 40 nm LP/RVT process.
USB 2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process
USB 2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process
USB 1.1 transceiver support crystal-less mode in USB system ; UMC 55nm eFlash Process
USB 1.1 transceiver support crystal-less mode in USB system ; UMC 55nm eFlash Process
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic Low Power Low-K Process
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic Low Power Low-K Process
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 0.11um HS/AE (AL Enhancement) Logic Process, without internal power clamping circuit
3.3V LVDS Transmitter 16~100MHz; 55nm SP/RVT LowK Logic Process
3.3V LVDS Transmitter 16~100MHz; 55nm SP/RVT LowK Logic Process
2.5V LVDS Transmitter 1.25Gbps; UMC 40nm LP LowK Logic Process.
2.5V LVDS Transmitter 1.25Gbps; UMC 40nm LP LowK Logic Process.
3.3V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process
3.3V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process
3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC process
3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC process
2.5V FPD-link LVDS Transmitter 16~178.6MHz; UMC 40nm LP Low-K process
2.5V FPD-link LVDS Transmitter 16~178.6MHz; UMC 40nm LP Low-K process
3.3v LVDS RX, 3 data lane and 1 clock lane using UMC 40nm LP/RVT LowK Logic Process
3.3v LVDS RX, 3 data lane and 1 clock lane using UMC 40nm LP/RVT LowK Logic Process
UMC 28nm HPC Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format
10 lane FXSLVTX030HH0L bias circuit ; UMC 40nm LP/RVT Logic Process
10 lane FXSLVTX030HH0L bias circuit ; UMC 40nm LP/RVT Logic Process
10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process
Input 80MHz-280MHz, DQS delay 3.125%-50% of FREF period, UMC 55nm SP/RVT Low-K logic process.
Input 80MHz-280MHz, DQS delay 3.125%-50% of FREF period, UMC 55nm SP/RVT Low-K logic process.
Input 80MHz-280MHz, DQS delay 6.25%-50% of FREF period, UMC 40nm LP/RVT Low-K logic process.
Input 80MHz-280MHz, DQS delay 6.25%-50% of FREF period, UMC 40nm LP/RVT Low-K logic process.
UMC 55nm LP/RVT Low-K logic process, Operating frequency 80MHz-320MHz, DQS delay 6.25%-50%.
UMC 55nm LP/RVT Low-K logic process, Operating frequency 80MHz-320MHz, DQS delay 6.25%-50%.
IP
USB1.1 PHY - HHGrace 110nm ULL
IP
The logiSLVDS_RX IP core enables easy interfacing of ultra high resolution Sony CMOS image sensors to image signal processing pip…