Fully compliant with PCI-SIG's PCIe v2.0 specification.
- Single-Protocol PHY
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Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
Fully compliant with PCI-SIG's PCIe v2.0 specification.
100BASE-T1 (OABR) Ethernet PHY IEEE 802.3bw Compliant
CT25204 is a physical layer for Open Alliance BroadR-Reach® and IEEE 802.3bw Ethernet communication within the car.
Ethernet 1G/2.5G BASE-X PCS/PMA or SGMII
The Xilinx Ethernet 1G/2.5G PCS/PMA or SGMII IP LogiCORE™ provides an Ethernet Physical Coding Sublayer (PCS) with a choice of ei…
This UHS2PHY IP solution for UHS-II interface that SD Association is working on the standardization as the new ultra high speed i…
This UHS2PHY IP solution for UHS-II interface that SD Association is working on the standardization as the new ultra high speed i…
SMIC 0.13um 1.2V/3.3V ONFI and MultIO combo IO
VeriSilicon SMIC 0.13μm ONFI COMBO I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing Interna…
10/100 Base-TX Fast Ethernet PHY; SMIC 40nm LL
SP-10_100_Ethernet-S40LL is a single-port DSP-based Fast Ethernet Transceiver.
TSMC 55nm USB2.0 Dual Role PHY
The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard.
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…
SMIC 0.18um Mini-LVDS Transmitter
The Mini-LVDS transmitter converts up to 48-bit or 36-bit RGB parallel data into 6-pair/3-pair of Mini-LVDS data stream that can …
10 Gigabit Ethernet PCS/PMA with FEC/Auto-Negotiation (10GBASE-KR)
The LogiCORE, 10 Gigabit Ethernet backpane PCS/PMA (10GBASE-KR) has been bundled with the 10G/25G Ethernet PCS/PMA with FEC/Auto-…
4 channel SERDES operating at up to 6.25Gbps for XAUI, RXAUI and SGMII (40nm TSMC)
PSI6254XRX is a 4 channel SERDES capable of providing XAUI (10G Attachment Unit Interface), RXAUI (10G Reduced Attachment Unit In…
SMIC 65nm Low Leakage LVDS Receiver
The LVDS Receiver converts up to 10 pairs of LVDS data streams into 70-bit of CMOS data and then feeds the data to the logic core…
XAUI 10Gb Ethernet Attachment Unit Interface
10Gb Ethernet Attachment Unit Interface or XAUI is a high-speed interconnect that offers reduced pin count and has the ability to…
10 Gigabit Ethernet PCS/PMA (10GBASE-R)
Included at no additional charge with Vivado® software Xilinx provides the 10 Gigabit Ethernet PCS/PMA (10GBASE-R) IP core with i…
IBM 65nm Mini-LVDS Transmitter
The Mini-LVDS transmitter converts up to 64-bit CMOS data into 16-pairs of Mini-LVDS data stream that can support Single-Link tra…
SMIC 65nm USB2.0 Dual Role PHY
The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard.
The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial…
The LVDS transmitter converts 28-bit data into 4-pair LVDS data stream.
The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard.