650M LVDS transmitter, 5 channel
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…
Overview
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution and Dual Link transmission between Host and Flat Panel Display with up to UXGA resolution. The IP converts 70-bit of CMOS/TTL data into LVDS data stream. The transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin.
Key features
- Supports 92MHz clock
- 35:5 data channel compression at data rate up to 650Mbps per channel
- Supports single pixel and dual pixel interfaces
- Converts 70 bits data to 10-pair LVDS data stream
- No external component required for PLL
- Clock edge selectable
- Compatible with TIA/EIA-644-A LVDS standard
- Power down mode
- Full industrial operating temperature range -40 ~ +85 °C
- SMIC18G Process (1.8V/3.3V)
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| SMIC | 180nm | G | — |
Specifications
Identity
Provider
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Frequently asked questions about Single-Protocol PHY IP
What is 650M LVDS transmitter, 5 channel?
650M LVDS transmitter, 5 channel is a Single-Protocol PHY IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for smic.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.