AMD Receives All Necessary Approvals for Proposed Acquisition of Xilinx
AMD (NASDAQ: AMD) today announced that it has received approval from all necessary authorities to proceed with the acquisition of Xilinx, Inc. (NASDAQ: XLNX).
Vendor:
Xilinx, Inc.
Category:
Single-Protocol PHY
10 Gigabit Ethernet PCS/PMA with FEC/Auto-Negotiation (10GBASE-KR)
The LogiCORE, 10 Gigabit Ethernet backpane PCS/PMA (10GBASE-KR) has been bundled with the 10G/25G Ethernet PCS/PMA with FEC/Auto-…
Overview
The LogiCORE, 10 Gigabit Ethernet backpane PCS/PMA (10GBASE-KR) has been bundled with the 10G/25G Ethernet PCS/PMA with FEC/Auto-Negotiation (25GBASE-KR).
The 10 Gigabit Ethernet backpane PCS/PMA (10GBASE-KR) is a Xilinx LogiCORE™ which has an optional FEC (forward error correction) and/or auto-negotiation protocol and link training allowing ultimate flexibility in your solution. The IP provides a XGMII interface to a 10 Gigabit Ethernet MAC and implements a 10.3125 Gbps serial single channel PHY over a backplane. The demand for 10G Ethernet is being driven in the data center as internet data traffic continues to grow. LAN application include Storage Area Networking (SAN), aggregation of 1G Ethernet links, and switch to switch links in the data center, equipment room or in different buildings.
NOTE: For UltraScale+ device support, refer to the 10G/25G Ethernet Subsystem
The 10 Gigabit Ethernet backpane PCS/PMA (10GBASE-KR) is a Xilinx LogiCORE™ which has an optional FEC (forward error correction) and/or auto-negotiation protocol and link training allowing ultimate flexibility in your solution. The IP provides a XGMII interface to a 10 Gigabit Ethernet MAC and implements a 10.3125 Gbps serial single channel PHY over a backplane. The demand for 10G Ethernet is being driven in the data center as internet data traffic continues to grow. LAN application include Storage Area Networking (SAN), aggregation of 1G Ethernet links, and switch to switch links in the data center, equipment room or in different buildings.
NOTE: For UltraScale+ device support, refer to the 10G/25G Ethernet Subsystem
Key features
- Designed to 10-Gigabit Ethernet specification IEEE 802.3-2012 clause 49, Forward Error Correction (FEC) clause 74, and Auto-Negotiation clause 73
- Optional Management Data Interface (MDIO) interface to manage PCS/PMA registers according to specification IEEE 802.3-2012 clause 45
- Available under the Xilinx Project Core License Agreement
- Supports LAN mode only
- SDR XGMII interface connects seamlessly to the Xilinx 10G Ethernet MAC
Specifications
Identity
Part Number
EF-DI-10GBASE-KR-PROJ
Vendor
Xilinx, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about Single-Protocol PHY IP
What is 10 Gigabit Ethernet PCS/PMA with FEC/Auto-Negotiation (10GBASE-KR)?
10 Gigabit Ethernet PCS/PMA with FEC/Auto-Negotiation (10GBASE-KR) is a Single-Protocol PHY IP core from Xilinx, Inc. listed on Semi IP Hub.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.