Vendor: Pico Semiconductor, Inc. Category: Single-Protocol PHY

4 channel SERDES operating at up to 6.25Gbps for XAUI, RXAUI and SGMII (40nm TSMC)

PSI6254XRX is a 4 channel SERDES capable of providing XAUI (10G Attachment Unit Interface), RXAUI (10G Reduced Attachment Unit In…

Overview

PSI6254XRX is a 4 channel SERDES capable of providing XAUI (10G Attachment Unit Interface), RXAUI (10G Reduced Attachment Unit Interface) and SGMII interfaces. Fig. 1 shows the top-level block diagram of this module in the XAUI mode where these 4 channels can receive and transmit data at the rate of 3.125Gbps each. The eye diagram at the TX output in the XAUI mode is shown in Fig. 2. Fig. 3 shows the top-level block diagram of the module in RXAUI mode where 2 channels are disabled and the other 2 operate at the rate of 6.25Gbps each. The eye diagram in the RXAUI mode is shown in Fig. 4. The 4 channels can also operate as 4 independent channels. Depending on the application, each transmitter can serialize 8, 10, 16 or 20 bit parallel data to a differential serial output and each receiver can de-serialize a differential serial input to 8, 10, 16 or 20 bit parallel output. A common block including a TXPLL provides clocks to the serializers in all channels. To improve signal integrity the common block also includes a calibration circuit providing control signals to make the transmitter output resistance and the receiver input resistance within 50Ω±5%.

Key features

  • 4 channel SERDES capable of operating at 1.25, 2.5-3.125 and 5-6.25Gbps.
  • Jitter generation and jitter tolerance exceed SGMII, XAUI and RXAUI specifications.
  • Serial output driver with calibrated on-chip termination resistor.
  • Selectable pre-emphasis level of signal at the output driver.
  • Serial input receiver with calibrated on-chip termination resistor.
  • Fixed equalization capability at the receiver input.
  • Near end and far end serial loopback.
  • Loss of signal detector.
  • Eye monitor
  • AC JTAG
  • Reference clock can be 25MHz or 156.25MHz.
  • 2 power supplies of 0.9V and 1.2V.
  • Only one external component is used (external resistor for termination resistor calibration).
  • TSMC 40nm G process.

Silicon Options

Foundry Node Process Maturity
TSMC 40nm G

Specifications

Identity

Part Number
PSI6254XRX
Vendor
Pico Semiconductor, Inc.
Type
Silicon IP

Provider

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Frequently asked questions about Single-Protocol PHY IP

What is 4 channel SERDES operating at up to 6.25Gbps for XAUI, RXAUI and SGMII (40nm TSMC)?

4 channel SERDES operating at up to 6.25Gbps for XAUI, RXAUI and SGMII (40nm TSMC) is a Single-Protocol PHY IP core from Pico Semiconductor, Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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