Overview
PSI6254XRX is a 4 channel SERDES capable of providing XAUI (10G Attachment Unit Interface), RXAUI (10G Reduced Attachment Unit Interface) and SGMII interfaces. Fig. 1 shows the top-level block diagram of this module in the XAUI mode where these 4 channels can receive and transmit data at the rate of 3.125Gbps each. The eye diagram at the TX output in the XAUI mode is shown in Fig. 2. Fig. 3 shows the top-level block diagram of the module in RXAUI mode where 2 channels are disabled and the other 2 operate at the rate of 6.25Gbps each. The eye diagram in the RXAUI mode is shown in Fig. 4. The 4 channels can also operate as 4 independent channels. Depending on the application, each transmitter can serialize 8, 10, 16 or 20 bit parallel data to a differential serial output and each receiver can de-serialize a differential serial input to 8, 10, 16 or 20 bit parallel output. A common block including a TXPLL provides clocks to the serializers in all channels. To improve signal integrity the common block also includes a calibration circuit providing control signals to make the transmitter output resistance and the receiver input resistance within 50Ω±5%.
Learn more about Single-Protocol PHY IP core
The IP is a GPON ONT SERDES capable of receiving serial data at the rate of 2.488Gbps and transmitting data at the rate of 1.244Gbps with an unmatched jitter performance. The IP core is capable of operating from 0.9V to 1.35V supply voltages and requires no external components.