Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: Single-Protocol PHY

IBM 65nm Mini-LVDS Transmitter

The Mini-LVDS transmitter converts up to 64-bit CMOS data into 16-pairs of Mini-LVDS data stream that can support Single-Link tra…

Overview

The Mini-LVDS transmitter converts up to 64-bit CMOS data into 16-pairs of Mini-LVDS data stream that can support Single-Link transmission with up to SXGA+ resolution, or Dual-Link transmission with up to UXGA resolution. This IP is suitable for Flat Panel Display applications.

Key features

  • Process: IBM 65nm 1.0V/2.5V cmos10sf, support metal option (TBD)
  • Logic input: total 64-bit data inputs, clock trigger edge selectable
  • Mini-LVDS output: Single-Link or Dual-Link; 8-channel data + SP + clock for each link
  • Clock freq: input 70M ~ 250MHz, output 140M ~ 500MHz (data mux 4:1)
  • Output data rate: max 1Gbps per channel
  • VOD and VCM adjustable
  • Link skew and channel skew adjustable
  • On-chip DLL supports SSC clock of central spread +/-5%, <150kHz
  • Individual power-down control for each link
  • Individual high-Z control for each output
  • Operating junction temperature: -40°C&#8804;TJ&#8804;+125°C

Silicon Options

Foundry Node Process Maturity
IBM 65nm LPe

Specifications

Identity

Part Number
I65GV25_MINILVDSTX_01
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP

Provider

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Frequently asked questions about Single-Protocol PHY IP

What is IBM 65nm Mini-LVDS Transmitter?

IBM 65nm Mini-LVDS Transmitter is a Single-Protocol PHY IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for ibm.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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