Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: Single-Protocol PHY

SMIC 0.13um 1.2V/3.3V ONFI and MultIO combo IO

VeriSilicon SMIC 0.13μm ONFI COMBO I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing Interna…

SMIC 130nm G Available on request View all specifications

Overview

VeriSilicon SMIC 0.13μm ONFI COMBO I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.13μm logic 1P8M Salicide 1.2/3.3V process. This library is fully compliant with the ONFI (Open NAND Flash Interface) 2.1 standard and LVCMOS and LVTTL IO with multiple IO power supply.

Key features

  • Process: Semiconductor Manufacturing International Corporation (SMIC) 0.13um Logic Salicide 1.2/3.3V process
  • Supply voltage:----1.5V~3.3V for I/O power supply;----1.2V core power supply
  • Power on sequence control for low leakage
  • Configurable output strength to support multIO nad ONFI
  • Selective output slew rate control
  • 1.8V ONFI pseudo-differential receiver with single pad

Silicon Options

Foundry Node Process Maturity
SMIC 130nm G Available on request

Specifications

Identity

Part Number
S13V33_MULTIO_ONFICOMBO_01
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP

Provider

Learn more about Single-Protocol PHY IP core

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Frequently asked questions about Single-Protocol PHY IP

What is SMIC 0.13um 1.2V/3.3V ONFI and MultIO combo IO?

SMIC 0.13um 1.2V/3.3V ONFI and MultIO combo IO is a Single-Protocol PHY IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for smic Available on request.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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