LVDS Deserializer IP
The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
Overview
The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components. Great care was taken to insure matching between the Data and Clock channels to maximize the deserializer margin. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
Key features
- 25-165 MHz clock support
- Up to 1.15 Gbps bandwidth
- Up to 5 Gbps data throughput
- Low power CMOS design
- Power Down mode
- Low swing LVDS devices for low EMI
- PLL requires no external components
- Programmable parallel data width
- Compatible with TIA/EIA-644 LVDS Standard
Block Diagram
Specifications
Identity
Files
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Provider
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Frequently asked questions about Single-Protocol PHY IP
What is LVDS Deserializer IP?
LVDS Deserializer IP is a Single-Protocol PHY IP core from Mixel, Inc. listed on Semi IP Hub.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.