Vendor: Mixel, Inc. Category: Single-Protocol PHY

LVDS Deserializer IP

The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.

Overview

The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components. Great care was taken to insure matching between the Data and Clock channels to maximize the deserializer margin. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.

Key features

  • 25-165 MHz clock support
  • Up to 1.15 Gbps bandwidth
  • Up to 5 Gbps data throughput
  • Low power CMOS design
  • Power Down mode
  • Low swing LVDS devices for low EMI
  • PLL requires no external components
  • Programmable parallel data width
  • Compatible with TIA/EIA-644 LVDS Standard

Block Diagram

Specifications

Identity

Part Number
MXL-DS-LVDS
Vendor
Mixel, Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

Learn more about Single-Protocol PHY IP core

Can MIPI and MDDI Co-Exist?

Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

MIPI deployment in ultra-low-power streaming sensors

This article focuses on low-power scenarios with streaming sensors connected to a processor via MIPI. After a short overview of low-duty cycle sensor principles, we explore how a streaming image sensor leverages those principles, show how one semiconductor company uses MIPI CSI-2® and D-PHY interfaces in their imaging solution, and touch on use cases for ultra-low-power streaming sensors deploying MIPI.

MIPI M-PHY takes center stage

The curtain is up and the M-PHY specification is taking center stage, positioned to handle the many different roles required for a faster, more reliable, physical interface layer (PHY Layer) on mobile devices.

MIPI Drives Performance for Next-Generation Displays

In this white paper, we will explore the history of MIPI display technology, (DSI and DSI-2), MIPI display markets, and the emerging bandwidth gap given the performance requirements of next- generation displays.

Frequently asked questions about Single-Protocol PHY IP

What is LVDS Deserializer IP?

LVDS Deserializer IP is a Single-Protocol PHY IP core from Mixel, Inc. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP