Vendor: Obsidian Technology Category: Single-Protocol PHY

LVDS Transceiver

OT3910bjc is a set of cells designed for implementing the transmitter, receiver and associated bias function for LVDS point to po…

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Overview

OT3910bjc is a set of cells designed for implementing the transmitter, receiver and associated bias function for LVDS point to point communication on the ams AMSC18 digital process. Compatible power pads are also provided.

The transmit driver cell translates 1.8V core logic signal levels to LVDS levels with a typical differential output swing of 350 mV. The receiver cell translates LVDS levels, with a typical differential input threshold of of above 100mV, to 1.8V core logic signal levels. A reference cell is also provided to produce appropriate bias currents voltage reference signals for the transmit and receive cells.

Key features

  • Meets or exceeds the TIA/EIA-644 LVDS standard.
  • Driver, Receiver, Bias, and Power cells included.
  • Greater than 400Mbs data rate.
  • 1.8V core voltage, 3.3V IO voltage.
  • Receive fault detection.
  • 0.2ns differential pulse skew.
  • 0.8ns receive propagation delay.

Block Diagram

OT3910bjc block diagram

Specifications

Identity

Part Number
OT3910bjc
Vendor
Obsidian Technology
Type
Silicon IP

Files

Product Sheet Download

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Provider

Contact Obsidian Technology

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Frequently asked questions about Single-Protocol PHY IP

What is LVDS Transceiver?

LVDS Transceiver is a Single-Protocol PHY IP core from Obsidian Technology listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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