Vendor: Logic Fruit Technologies Category: Single-Protocol PHY

PCIe GEN6 PHY IP

The PCIe GEN6 PHY IP achieves data rates up to 64GT/s per lane with PAM4 signaling thereby delivering reliable performance for hi…

Overview

The PCIe GEN6 PHY IP achieves data rates up to 64GT/s per lane with PAM4 signaling thereby delivering reliable performance for high-speed data transfer. It supports advanced applications, including AI/ML, High-Performance Computing, and next-generation storage solutions.

Key features

  • Supports PRBS (Pseudo Random Binary Sequence) testing including loopback modes
  • Supports different power states as defined in PCIe PHY specification
  • Supports 100MHz common reference clock between RC and EP
  • Supports the PCIe Gen6 compliance/modified compliance (PCIe base 6.2 sections 4.2.14-15)
  • Supports 52UI jitter measurement (PCIe base 6.2 section 4.2.16)
  • Supports High swing toggle (PCIe base 6.2 section 4.2.17)

Block Diagram

PCIe GEN6 PHY IP block diagram

Specifications

Identity

Part Number
PCIe GEN6 PHY IP
Vendor
Logic Fruit Technologies
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Single-Protocol PHY IP core

Frequently asked questions about Single-Protocol PHY IP

What is PCIe GEN6 PHY IP?

PCIe GEN6 PHY IP is a Single-Protocol PHY IP core from Logic Fruit Technologies listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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