Vendor: Altera Category: Single-Protocol PHY

40G Ethernet MAC and PHY FPGA IP Core

The 40G Ethernet MAC and PHY FPGA IP core offers IEEE 802.3ba-2010.

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Overview

The 40G Ethernet MAC and PHY FPGA IP core offers IEEE 802.3ba-2010. 40 Gbps Ethernet is an industry standard and is compliant for media access control (MAC) and PHY (PCS+PMA) functions. It enables an FPGA to interface to another device over a copper or optical transceiver module. The IP supports IEEE 1588 v2 standard with two-step timestamping as well as backplane capability on a variety of Stratix® or Arria® FPGAs.

Key features

  • Compliant with the IEEE 802.3ba-2010 40 Gbps Ethernet standard.
  • XLAUI physical medium attachment (PMA) hard IP and external interface consisting of serial transceiver lanes each operating at 10.3125 Gbps.
  • 40GbE physical coding sublayer (PCS) soft IP implemented in the FPGA fabric.
  • 40GbE MAC soft IP with configurable feature set.
  • Supported options:
  • 40GbE.
  • MAC+PHY, PHY-only or MAC-only.
  • Transmitter plus receiver (full-duplex), transmitter-only or receiver-only.
  • Hardware verified to support full 40 Gbps wire speed traffic.
  • PCS bit error rate (BER) monitor.
  • Programmable PCS test pattern generator and checker.
  • Deficit idle count (DIC).
  • Automatic Ethernet flow control.
  • Programmable MAC transmitter (TX) cyclic redundancy check (CRC) insertion and receiver (RX) CRC removal.
  • Programmable maximum receive frame length up to 9,600 bytes.
  • Programmable MAC address and receiver (RX) packet filtering based on MAC address.
  • Promiscuous (transparent) and non-promiscuous (filtered) MAC operation modes.
  • Programmable MAC received frame filtering with CRC, oversized and undersized frame error.
  • Receive filtering of control frames (pause control and/or non-pause control).
  • Receive user-controllable pad removal.
  • Transmit automatic pad insertion.
  • Statistics status output signals for external statistics counters implementation.
  • Optional 64-bit statistics counters module for RMON (RFC 2819), Ethernet-type MIB (RFC 3635), and interface group MIB (RFC 2863).
  • Programmable link fault signaling.
  • Optional preamble pass through.
  • Avalon® streaming interface (Avalon-ST) for MAC datapath to client application with the start of packet (SOP) in 64-bit lane 0's most significant byte (MSB) when adapter option is used (256 bits at 312.5+ MHz).
  • Custom streaming interface with SOP possible on any 64-bit lane MSB when adapter option is not used.
  • Avalon® Memory Mapped (Avalon-MM) 32-bit interface for control and monitoring of MAC, PCS, PMA, and external optical module.
  • Management data input/output (MDIO) or 2-wire serial interfaces for managing different optical modules.
  • Passed functional and performance tests with 40/100Gb Ethernet test equipment.

Block Diagram

40G Ethernet MAC and PHY FPGA IP Core block diagram

Specifications

Identity

Part Number
40G Ethernet MAC and PHY FPGA IP Core
Vendor
Altera
Type
Silicon IP

Files

Product Sheet Download

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Provider

Altera
HQ: USA
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Frequently asked questions about Single-Protocol PHY IP

What is 40G Ethernet MAC and PHY FPGA IP Core?

40G Ethernet MAC and PHY FPGA IP Core is a Single-Protocol PHY IP core from Altera listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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